2026-09-18T21:41:49Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/333322022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Michael H. Perrott.
Park, Matthew (Matthew J.)
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-07-13T15:15:59Z
2006-07-13T15:15:59Z
2005
2005
http://hdl.handle.net/1721.1/33332
62326142
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
In title on t.p., [Sigma] and [Delta] appear as the upper-case Greek letters.
Includes bibliographical references (p. 87-89).
This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power.
by Matthew Park.
M.Eng.
89 p.
3414261 bytes
3417910 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="ad8f0f3a-c5ed-4530-97ae-76dadfa9e204">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>An optical-electrical sub-sampling down-conversion receiver with continuous-time [Sigma] [Delta] modulation</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2005</PublicationDate>
<Authors>
<Author>
<DisplayName>Park, Matthew (Matthew J.)</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>This thesis describes the design and implementation of an optical-electrical sub-sampling down-conversion receiver that employs [Sigma] [Delta] modulation. Accurate sub-sampling of an electrical RF signal in the optical domain is achieved by using a low-jitter mode-locked-laser and a high-bandwidth interferometer. The sub-sampled information is then digitized by an optical-electrical continuous-time (CT) [Sigma] [Delta] analog- to-digital converter (ADC). Here, photodiodes and low-jitter pulses from the mode- locked-laser are leveraged to perform signal clocking and quantizer pre-amplification, overcoming digital-to-analog converter (DAC) clock jitter and quantizer metastability issues that plague traditional electronic implementations. The optical-electrical converter achieves 76.5 dB of SNR (12.4 ENOB) with a 1 MHz signal bandwidth and a sampling rate of 780 MHz. The chip was implemented using a standard bulk 0.18 [mu]m CMOS process from National Semiconductor, occupies a total area of 3 mm2, and consumes 45 mW of power.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>