2026-09-19T01:46:22Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/333362022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anant Agarwal.
Ramaswamy, Satish
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-07-13T15:16:18Z
2006-07-13T15:16:18Z
2005
2005
http://hdl.handle.net/1721.1/33336
62367606
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 181-182).
Caches help reduce the effect of long-latency memory requests, by providing a high speed data-path to local memory. However, in multi-processor systems utilizing shared memory, cache coherence protocols are necessary to ensure sequential consistency. Of the multiple coherence protocols developed, the scalability of directory-based schemes makes them ideal for RAW's architecture [1]. Although one such system has been demonstrated as a proof-of-concept, it lacks the ability to meet the requirements of load-intensive, high performance applications. It further provides the application developer with no programming constructs to easily leverage the system. This thesis further develops shared memory support for RAW, by bringing greater programmability and performance to shared memory applications. In doing so, it reveals that shared memory is a practical programming paradigm for developing parallel applications on the RAW architecture.
by Satish Ramaswamy.
M.Eng.
182 p.
6911163 bytes
6918817 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Optimizing directory-based cache coherence on the RAW architecture
Thesis
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