<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T20:41:20Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/34353" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/34353</identifier><datestamp>2022-01-13T07:54:29Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131023</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">L. Rafael Reif and Robert K. Reich.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Tyrrell, Brian (Brian Matthew)</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2006-11-06T18:17:02Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2006-11-06T18:17:02Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2004</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2004</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">http://hdl.handle.net/1721.1/34353</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">70078282</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (p. 153-159).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI fabrication and the fabrication complexity of 3-D integration, analysis of the design and process tradeoffs for a particular application is essential. An architectural and topological design tool is presented that enables the high-level analysis and optimization of sensor architectures targeted to a variety of 3-D VLSI process options. This design tool is based on an inference chain evaluation framework, and allows for a high-level structural representation of a circuit architecture to be considered in conjunction with low-level process models. Approximation strategies for projecting circuit area and performance are incorporated into the inference chain relations.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Brian Tyrrell.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">S.M.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">159 p.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent">8060895 bytes</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent">8068367 bytes</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="mimetype">application/pdf</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="mimetype">application/pdf</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso" lang="en_US">eng</dim:field>
   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Development of an architectural design tool for 3-D VLSI sensors</dim:field>
   <dim:field mdschema="dc" element="type" lang="en_US">Thesis</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="mimetype">application/pdf</dim:field>
   <dim:field mdschema="dspace" element="authorsordered">false</dim:field>
   <dim:field mdschema="dspace" element="entity" qualifier="type">Publication</dim:field>
   <dim:field mdschema="others" element="access-status">unknown</dim:field>
   <dim:field mdschema="others" element="access-status">unknown</dim:field>
   <dim:field mdschema="cerif" element="openaire" authority="" confidence="-1">&lt;Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="d84444ed-b26f-459f-b7c9-4e859c302f2c">
	&lt;Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843&lt;/Type>
	&lt;Language>eng&lt;/Language>
   	&lt;Title>Development of an architectural design tool for 3-D VLSI sensors&lt;/Title>
   	&lt;PublishedIn>
    	&lt;Publication>
      	&lt;/Publication>
   	&lt;/PublishedIn>
   	&lt;PublicationDate>2004&lt;/PublicationDate>
   	&lt;Authors>
      	&lt;Author>
        	&lt;DisplayName>Tyrrell, Brian (Brian Matthew)&lt;/DisplayName>
         	&lt;Affiliation>
         		&lt;OrgUnit>
         		&lt;/OrgUnit>
         	&lt;/Affiliation>
      	&lt;/Author>
	&lt;/Authors>
   	&lt;Editors>
	&lt;/Editors>
    &lt;Publishers>
        &lt;Publisher>
            &lt;DisplayName>Massachusetts Institute of Technology&lt;/DisplayName>
            &lt;OrgUnit />
        &lt;/Publisher>
    &lt;/Publishers>
    &lt;License>http://dspace.mit.edu/handle/1721.1/7582&lt;/License>
    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI fabrication and the fabrication complexity of 3-D integration, analysis of the design and process tradeoffs for a particular application is essential. An architectural and topological design tool is presented that enables the high-level analysis and optimization of sensor architectures targeted to a variety of 3-D VLSI process options. This design tool is based on an inference chain evaluation framework, and allows for a high-level structural representation of a circuit architecture to be considered in conjunction with low-level process models. Approximation strategies for projecting circuit area and performance are incorporated into the inference chain relations.&lt;/Abstract>
	&lt;Access xmlns="http://purl.org/coar/access_right" 
    >
    &lt;/Access>
&lt;/Publication>
</dim:field>
</dim:dim>
</metadata></record></GetRecord></OAI-PMH>