2026-09-19T14:45:24Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/343652022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anantha P. Chandrakasan.
Lajevardi, Payam
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2006-11-07T11:48:37Z
2006-11-07T11:48:37Z
2005
2005
http://hdl.handle.net/1721.1/34365
70079187
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 67-71).
The intercornnect delay in the new generations of integrated circuits imposes a significant limitation on the performance of ICs. 3-Dimensional integration of integrated circuits had been proposed to improve the interconnect delay. In this research, the effect of 3-D integration on the delay and power of FPGA chips is analyzed. Different physical partitioning of FPGAs is proposed for 3-D integration and one is analyzed in detail. The size of 3-D FPGAs differs from the size of 2-D FPGAs because of the overhead of 3-1D connections and different connectivity in switch blocks. Layout of 2-D and 3-D FPGAs is prepared to compare their size. To compare 3-D and 2-D FPGAs properly, two basic routability metrics are proposed to compare the routability of 3-D and 2-D circuits. Then, the delay of a 2-D and a 3-D FPGA with the same routability is compared. It is shown that 20%-29% delay improvement can be achieved by using a 3-D FPGA. In addition, the power consumption of 3-D FPGAs is analyzed. It is shown that if the supply voltage and the operating frequency of a 3-D FPGA are held to be the same as a 2-D FPGA, 17%-22% power improvement can be achieved. However, 3-D FPGAs can run faster since their delay is improved as well. If the delay improvement is traded off for more power saving by lowering the supply voltage, 35%-39% power improvement can be expected. Finally, to reduce the magnitude of supply current required for an integrated circuit, the method of stacking logic circuits is analyzed. This method requires level conversion between different supply domains. In this research, the architecture of several level converters are described and their delays are compared.
by Payam Lajevardi.
S.M.
71 p.
3312533 bytes
3315175 bytes
application/pdf
application/pdf
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Design of a 3-dimension FPGA
Design of a 3D Field Programmable Gate Array
Thesis
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