2026-09-19T03:26:48Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/365802022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Srinivas Devadas.
Sánchez, Clara
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2007-03-12T17:33:35Z
2007-03-12T17:33:35Z
1995
1995
http://hdl.handle.net/1721.1/36580
33343502
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.
Includes bibliographical references (leaves 33-35).
by Clara Sánchez.
M.Eng.
35 leaves
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science
BIST test pattern generator based on partitioning circuit inputs
Thesis
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