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Krste Asanović. Liu, Rose F. (Rose Frances) Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2007-03-12T17:54:09Z 2007-03-12T17:54:09Z 2005 2005 http://hdl.handle.net/1721.1/36792 79628828 Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005. Includes bibliographical references (p. 73-74). In the early stages of processor design, computer architects rely heavily on simulation to explore a very large design space. Although detailed microarchitectural simulation is effective and widely used for evaluating different processor configurations, long simulation times and a limited time-to-market severely constrain the number of design points explored. This thesis presents AXCIS, a framework for fast and accurate early-stage design space exploration. Using instruction segments, a new primitive for extracting and representing simulation-critical data from full dynamic traces, AXCIS compresses the full dynamic trace into a table of canonical instruction segments (CIST). CISTs are not only small, but also very representative of the dynamic trace. Therefore, given a CIST and a processor configuration, AXCIS can quickly and accurately estimate performance metrics such as instructions per cycle (IPC). This thesis applies AXCIS to in-order superscalar processors, which are becoming more popular with the emergence of chip multiprocessors (CMP). For 24 SPEC CPU2000 benchmarks and all simulated configurations, AXCIS achieves an average IPC error of 2.6% and is over four orders of magnitude faster than conventional detailed simulation. (cont.) While cycle-accurate simulators can take many hours to simulate billions of dynamic instructions, AXCIS can complete the same simulation on the corresponding CIST within seconds. by Rose F. Liu. M.Eng. 74 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. AXCIS : rapid processor architectural exploration using canonical instruction segments Rapid processor architectural exploration using canonical instruction segments Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="d5d501a7-2434-4c5b-924a-181cb19e0a1d"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>AXCIS : rapid processor architectural exploration using canonical instruction segments</Title> <Subtitle>Rapid processor architectural exploration using canonical instruction segments</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2005</PublicationDate> <Authors> <Author> <DisplayName>Liu, Rose F. (Rose Frances)</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>In the early stages of processor design, computer architects rely heavily on simulation to explore a very large design space. Although detailed microarchitectural simulation is effective and widely used for evaluating different processor configurations, long simulation times and a limited time-to-market severely constrain the number of design points explored. This thesis presents AXCIS, a framework for fast and accurate early-stage design space exploration. Using instruction segments, a new primitive for extracting and representing simulation-critical data from full dynamic traces, AXCIS compresses the full dynamic trace into a table of canonical instruction segments (CIST). CISTs are not only small, but also very representative of the dynamic trace. Therefore, given a CIST and a processor configuration, AXCIS can quickly and accurately estimate performance metrics such as instructions per cycle (IPC). This thesis applies AXCIS to in-order superscalar processors, which are becoming more popular with the emergence of chip multiprocessors (CMP). For 24 SPEC CPU2000 benchmarks and all simulated configurations, AXCIS achieves an average IPC error of 2.6% and is over four orders of magnitude faster than conventional detailed simulation.</Abstract> <Abstract>(cont.) While cycle-accurate simulators can take many hours to simulate billions of dynamic instructions, AXCIS can complete the same simulation on the corresponding CIST within seconds.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>