2026-09-19T08:22:51Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/367952022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Krste Asanović.
Bhalodia, Vimal
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2007-03-12T17:54:27Z
2007-03-12T17:54:27Z
2005
2005
http://hdl.handle.net/1721.1/36795
79635922
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 51).
To address the needs of the next generation of low-power systems, DDR2 SDRAM offers a number of low-power modes with various performance and power consumption tradeoffs. The SCALE DRAM Subsystem is an energy-aware DRAM system with various system policies that make use of these modes. In this thesis, we design and implement a DDR2 DRAM controller and test a version of the SCALE DRAM Subsystem in hardware. Power measurements from the actual DRAM chips are taken and compared to datasheet derived values, and an analysis of the DRAM refresh requirements is performed. Some notable power consumption results include active powerdown being much closer to precharge powerdown and reads taking much less current than the datasheet indicates. In addition, based on the refresh tests, a system that powers down at least 12.3s for each 32MB of traffic can save power using delayed refresh and ECC data encoding.
by Vimal Bhalodia.
M.Eng.
51 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
SCALE DRAM subsystem power analysis
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="eb8379dc-c2fe-4df9-8b40-b409ea52d39f">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>SCALE DRAM subsystem power analysis</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2005</PublicationDate>
<Authors>
<Author>
<DisplayName>Bhalodia, Vimal</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>To address the needs of the next generation of low-power systems, DDR2 SDRAM offers a number of low-power modes with various performance and power consumption tradeoffs. The SCALE DRAM Subsystem is an energy-aware DRAM system with various system policies that make use of these modes. In this thesis, we design and implement a DDR2 DRAM controller and test a version of the SCALE DRAM Subsystem in hardware. Power measurements from the actual DRAM chips are taken and compared to datasheet derived values, and an analysis of the DRAM refresh requirements is performed. Some notable power consumption results include active powerdown being much closer to precharge powerdown and reads taking much less current than the datasheet indicates. In addition, based on the refresh tests, a system that powers down at least 12.3s for each 32MB of traffic can save power using delayed refresh and ECC data encoding.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>