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Duane S. Boning. Abrokwah, Kwaku O Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2007-04-03T17:06:23Z 2007-04-03T17:06:23Z 2006 2006 http://hdl.handle.net/1721.1/37054 79649392 Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. Leaf 108 blank. Includes bibliographical references (leaves 106-107). A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent non-uniformities arise in plasma etching due to microloading and RIE lag. This thesis contributes a semi-empirical methodology for capturing and modeling microloading, RIE lag, and related pattern dependent effects. We apply this methodology to the study of interconnect trench etching, and show that an integrated model is able to predict both pattern density and feature size dependent non-uniformities in trench depth. Previous studies of variation in plasma etching have characterized microloading (due to pattern density), and RIE lag (aspect ratio dependent etching or ARDE) as distinct causes of etch non-uniformity for individual features. In contrast to these previous works, we present here a characterization and computational methodology for predicting IC etch variation on a chip scale that integrates both layout pattern density and feature scale or ARDE dependencies. The proposed integrated model performs well in predicting etch variation as compared to a pattern density only or feature scale only model. by Kwaku O. Abrokwah. M.Eng. 108 leaves eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Characterization and modeling of plasma etch pattern dependencies in integrated circuits Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="80b25708-e683-4645-b6ea-43e75b6ab555"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Characterization and modeling of plasma etch pattern dependencies in integrated circuits</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2006</PublicationDate> <Authors> <Author> <DisplayName>Abrokwah, Kwaku O</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent non-uniformities arise in plasma etching due to microloading and RIE lag. This thesis contributes a semi-empirical methodology for capturing and modeling microloading, RIE lag, and related pattern dependent effects. We apply this methodology to the study of interconnect trench etching, and show that an integrated model is able to predict both pattern density and feature size dependent non-uniformities in trench depth. Previous studies of variation in plasma etching have characterized microloading (due to pattern density), and RIE lag (aspect ratio dependent etching or ARDE) as distinct causes of etch non-uniformity for individual features. In contrast to these previous works, we present here a characterization and computational methodology for predicting IC etch variation on a chip scale that integrates both layout pattern density and feature scale or ARDE dependencies. The proposed integrated model performs well in predicting etch variation as compared to a pattern density only or feature scale only model.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>