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Hae-Seung Lee and Charles G. Sodini. Sepke, Todd C. (Todd Christopher), 1975- Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2007-09-28T13:09:26Z 2007-09-28T13:09:26Z 2006 2007 http://hdl.handle.net/1721.1/38925 164897493 Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007. Includes bibliographical references (p. 177-182). The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that eliminates the need for high gain op-amps in the signal path is proposed. The CBSC technique applies to switched-capacitor circuits in general and is compatible with most known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a 0.18 [mu]m CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5 mW of power. Techniques for the noise analysis of comparator-based systems are presented. Non-stationary noise analysis techniques are applied to circuit analysis problems for white noise sources in a framework consistent with the more familiar wide-sense-stationary techniques. The design of a low-noise threshold detection comparator using a preamplifier is discussed. (cont.) Assuming the preamplifier output is reset between decisions, it is shown that. for a given noise and speed requirement, a band-limiting preamplifier is the lowest power implementation. Noise analysis techniques are applied to the prototype CBSC gain stage to arrive at, a theoretical noise power spectral density (PSD) estimate for the prototype pipeline ADC. Theoretical predictions and measured results of the input referred noise PSD for the prototype are compared showing that the noise contribution of the preamplifier dominates the overall noise performance. by Todd C. Sepke. Ph.D. 182 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Comparator design and analysis for comparator-based switched-capacitor circuits Comparator design and analysis for CBSC Thesis application/pdf Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="70efa8c8-d367-4d79-851b-3fadd3574062"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Comparator design and analysis for comparator-based switched-capacitor circuits</Title> <Subtitle>Comparator design and analysis for CBSC</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2007</PublicationDate> <Authors> <Author> <DisplayName>Sepke, Todd C. (Todd Christopher), 1975-</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC) technique that eliminates the need for high gain op-amps in the signal path is proposed. The CBSC technique applies to switched-capacitor circuits in general and is compatible with most known architectures. A prototype 1.5 b/stage pipeline ADC implemented in a 0.18 [mu]m CMOS process is presented that operates at 7.9 MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5 mW of power. Techniques for the noise analysis of comparator-based systems are presented. Non-stationary noise analysis techniques are applied to circuit analysis problems for white noise sources in a framework consistent with the more familiar wide-sense-stationary techniques. The design of a low-noise threshold detection comparator using a preamplifier is discussed.</Abstract> <Abstract>(cont.) Assuming the preamplifier output is reset between decisions, it is shown that. for a given noise and speed requirement, a band-limiting preamplifier is the lowest power implementation. Noise analysis techniques are applied to the prototype CBSC gain stage to arrive at, a theoretical noise power spectral density (PSD) estimate for the prototype pipeline ADC. Theoretical predictions and measured results of the input referred noise PSD for the prototype are compared showing that the noise contribution of the preamplifier dominates the overall noise performance.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>