2026-09-18T23:38:44Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/396862022-01-28T19:24:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Stephen Graves and Duane Boning.
Subramanian, Nima
Leaders for Manufacturing Program.
Leaders for Manufacturing Program at MIT
Massachusetts Institute of Technology. Department of Mechanical Engineering
Sloan School of Management
2007-12-07T16:07:03Z
2007-12-07T16:07:03Z
2007
2007
http://hdl.handle.net/1721.1/39686
175304158
Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; in conjunction with the Leaders for Manufacturing Program at MIT, 2007.
Includes bibliographical references (p. 60-61).
Intel Corporation's Fab17 located at Hudson, MA underwent a large scale manufacturing ramp-up, increasing its production volume by over 50%. As a result of this manufacturing ramp-up, the factory is faced with various capacity issues. These capacity issues along with current work-in-progress inventory (WIP) management strategies lead to an unbalanced inventory flow within the factory. The unbalanced WIP flow results in wafers accumulating in front of certain operations/areas. This WIP accumulation or "WIP bubbles" creates unexpected demand for the various resources on the shop floor, putting an undue strain on them. This strain is felt the most in the bottleneck area. The objective of this project is to develop a sustainable solution methodology to alleviate the strain on the bottleneck. The scope of this project falls under Fab 17's lean manufacturing organization, known as the manufacturing excellence (mX) group, and, the analysis used in this internship utilizes lean manufacturing concepts and principles. The solution methodology analyzes the wafer fabrication process in layers rather than in segments. This approach clarifies WIP movement and identifies problem areas that cause WIP bubbles. Further, the thesis applies the concept of production leveling to wafer fabrication in order to alleviate (and eliminate) the pressure on the bottleneck.
by Nima Subramanian.
S.M.
M.B.A.
61 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Sloan School of Management.
Mechanical Engineering.
Leaders for Manufacturing Program.
Lean manufacturing in a semiconductor environment : production leveling
Thesis
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<Abstract>Intel Corporation's Fab17 located at Hudson, MA underwent a large scale manufacturing ramp-up, increasing its production volume by over 50%. As a result of this manufacturing ramp-up, the factory is faced with various capacity issues. These capacity issues along with current work-in-progress inventory (WIP) management strategies lead to an unbalanced inventory flow within the factory. The unbalanced WIP flow results in wafers accumulating in front of certain operations/areas. This WIP accumulation or "WIP bubbles" creates unexpected demand for the various resources on the shop floor, putting an undue strain on them. This strain is felt the most in the bottleneck area. The objective of this project is to develop a sustainable solution methodology to alleviate the strain on the bottleneck. The scope of this project falls under Fab 17's lean manufacturing organization, known as the manufacturing excellence (mX) group, and, the analysis used in this internship utilizes lean manufacturing concepts and principles. The solution methodology analyzes the wafer fabrication process in layers rather than in segments. This approach clarifies WIP movement and identifies problem areas that cause WIP bubbles. Further, the thesis applies the concept of production leveling to wafer fabrication in order to alleviate (and eliminate) the pressure on the bottleneck.</Abstract>
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