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Hae-Seung Lee and Charles G. Sodini. Fiorenza, John Kenneth, 1977- Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2008-02-27T20:37:28Z 2008-02-27T20:37:28Z 2007 2007 http://hdl.handle.net/1721.1/40312 191822802 Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007. This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. Includes bibliographical references (leaves 112-115). A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-amps, comparators suffer less from the negative effects of scaled CMOS. The technique is applicable to a broad class of sampled-data circuits including analog-to-digital converters, digital-to-analog converters, sample-and-holds, integrators and filters. As a proof of concept the technique is demonstrated in the design of a pipelined analog-to-digital converter. The prototype CBSC 1.5 b/stage pipelined ADC implemented in a 0.18 [mu]m CMOS process operates at 7.9MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5mW of power. Sources of offset and nonlinearity are identified and analyzed. The analysis reveals the potential of the CBSC technique for lower power dissipation and provides design guidelines for energy efficient comparator-based switched-capacitor circuit design. by John K. Fiorenza. Ph.D. 136 leaves eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. A comparator-based switched-capacitor pipelined analog-to-digital converter CBSC pipelined analog-to-digital converter Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="f74fd3ef-77da-43c8-9abc-522f1009a668"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>A comparator-based switched-capacitor pipelined analog-to-digital converter</Title> <Subtitle>CBSC pipelined analog-to-digital converter</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2007</PublicationDate> <Authors> <Author> <DisplayName>Fiorenza, John Kenneth, 1977-</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>A new comparator-based switched-capacitor(CBSC) technique is proposed that eliminates the need for high gain op-amps in switched-capacitor circuits. The CBSC technique replaces the op-amp in switched-capacitor circuits with a comparator and a current source. Compared to op-amps, comparators suffer less from the negative effects of scaled CMOS. The technique is applicable to a broad class of sampled-data circuits including analog-to-digital converters, digital-to-analog converters, sample-and-holds, integrators and filters. As a proof of concept the technique is demonstrated in the design of a pipelined analog-to-digital converter. The prototype CBSC 1.5 b/stage pipelined ADC implemented in a 0.18 [mu]m CMOS process operates at 7.9MHz, achieves 8.6 effective bits of accuracy, and consumes 2.5mW of power. Sources of offset and nonlinearity are identified and analyzed. The analysis reveals the potential of the CBSC technique for lower power dissipation and provides design guidelines for energy efficient comparator-based switched-capacitor circuit design.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>