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Doug La Porte and Charles G. Sodini. Medina, Rafael A Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2008-05-19T16:00:31Z 2008-05-19T16:00:31Z 2006 2006 http://hdl.handle.net/1721.1/41610 216831947 Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006. Includes bibliographical references (leaves 74-75). Low noise oscillators are critical building blocks in a wide range of commercial electronics. Increased levels of integration have created a strong need for integrated oscillator solutions despite generally inferior noise performance. The development of non-linear noise models that can accurately and efficiently predict noise in ring oscillators aids designers in optimizing noise performance in integrated oscillator solutions. Extending a piecewise constant model of noise in an oscillator and the resulting timing jitter reveals how the noise at the oscillator nodes changes during each portion of the cycle. The model can then be used to examine the effects of changing various process and design parameters such as threshold voltages and the effective stage gain. This analysis tool provides a means for designers to evaluate potential improvements of their oscillator design. In some cases approximate analytic solutions can be found that provide better insight into the timing jitter. A simple differential oscillator design illustrates the use of this analysis. The oscillator achieves an analog tuning range of 259MHz-314MHz (extendable with switched capacitors) with a normalized jitter of 102ppm. by Rafael A. Medina. M.Eng. 75 leaves eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Monolithic low phase noise oscillators for moderate frequency applications Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="adbfc196-7b76-4734-a5d1-efd72bcf8c5e"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Monolithic low phase noise oscillators for moderate frequency applications</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2006</PublicationDate> <Authors> <Author> <DisplayName>Medina, Rafael A</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>Low noise oscillators are critical building blocks in a wide range of commercial electronics. Increased levels of integration have created a strong need for integrated oscillator solutions despite generally inferior noise performance. The development of non-linear noise models that can accurately and efficiently predict noise in ring oscillators aids designers in optimizing noise performance in integrated oscillator solutions. Extending a piecewise constant model of noise in an oscillator and the resulting timing jitter reveals how the noise at the oscillator nodes changes during each portion of the cycle. The model can then be used to examine the effects of changing various process and design parameters such as threshold voltages and the effective stage gain. This analysis tool provides a means for designers to evaluate potential improvements of their oscillator design. In some cases approximate analytic solutions can be found that provide better insight into the timing jitter. A simple differential oscillator design illustrates the use of this analysis. The oscillator achieves an analog tuning range of 259MHz-314MHz (extendable with switched capacitors) with a normalized jitter of 102ppm.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>