<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-18T23:56:52Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/41640" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/41640</identifier><datestamp>2022-01-13T07:54:29Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131023</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">David J. Carter and Henry I. Smith.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Fucetola, Corey Patrick</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2008-05-19T16:04:10Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2008-05-19T16:04:10Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2007</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2007</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">http://hdl.handle.net/1721.1/41640</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">219682796</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (p. 78-80).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">Conformable Contact Lithography enables researchers to attain high-resolution lithographic patterning at manageable cost. This thesis characterizes the minimum resolvable feature size and process latitude of Conformable Contact Lithography. Beginning with a review of current lithographic patterning techniques, choice of Conformable Contract Lithography as an exposure technique is discussed. A design for a trilayer stack that optimizes optical properties is established using experimental and simulated reflectance data to choose appropriate stack film thicknesses. The simulated process latitude is constructed using electromagnetic simulations of grating patterns. Image analysis of experimentally-exposed diffraction grating patterns is described and used to characterize the effect of exposure dose on printed linewidth. The resulting simulated and experimental process latitudes for printed gratings are presented for masks utilizing protruding chrome lines and embedded chrome lines. Experimental and simulated reflectance for single-layer and bilayer film stacks are compared to yield an optimized trilayer stack design of 225nm of anti-reflection-coating chemically separated from the resist by 70nm of evaporated silicon oxide. This design results in less than 1.5% back-reflection from the oxide into the resist for 10% film thickness variation. Finite-difference time-domain simulations are optimized by comparing higher variable-resolution, more realistic simulations to more efficient, lower variable-resolution simulations. Building on the trilayer stack and optimal simulation specification, simulated exposures of diffraction gratings are analyzed assuming a clipping model of development. Exposures of dense grating patterns with two geometries are performed on trilayer-stack-coated silicon wafers for a range of doses.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">(cont.) Transferred grating patterns are analyzed to establish the effect of exposure dose on printed linewidth. A 5% experimental process latitude is achieved at a printed linewidth tolerance of ±15% for the embedded chrome mask exposures and of 25% for the protruding chrome mask exposures. Within the resist, contrast is higher at smaller gratings using the embedded mask.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Corey Patrick Fucetola.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">M.Eng.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">80 p.</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso" lang="en_US">eng</dim:field>
   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">M.I.T. theses are protected by 
copyright. They may be viewed from this source for any purpose, but 
reproduction or distribution in any format is prohibited without written 
permission. See provided URL for inquiries about permission.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri" lang="en_US">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Resolution limits and process latitude of comformable contact nano-lithography</dim:field>
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   	&lt;Title>Resolution limits and process latitude of comformable contact nano-lithography&lt;/Title>
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   	&lt;PublicationDate>2007&lt;/PublicationDate>
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        	&lt;DisplayName>Fucetola, Corey Patrick&lt;/DisplayName>
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    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>Conformable Contact Lithography enables researchers to attain high-resolution lithographic patterning at manageable cost. This thesis characterizes the minimum resolvable feature size and process latitude of Conformable Contact Lithography. Beginning with a review of current lithographic patterning techniques, choice of Conformable Contract Lithography as an exposure technique is discussed. A design for a trilayer stack that optimizes optical properties is established using experimental and simulated reflectance data to choose appropriate stack film thicknesses. The simulated process latitude is constructed using electromagnetic simulations of grating patterns. Image analysis of experimentally-exposed diffraction grating patterns is described and used to characterize the effect of exposure dose on printed linewidth. The resulting simulated and experimental process latitudes for printed gratings are presented for masks utilizing protruding chrome lines and embedded chrome lines. Experimental and simulated reflectance for single-layer and bilayer film stacks are compared to yield an optimized trilayer stack design of 225nm of anti-reflection-coating chemically separated from the resist by 70nm of evaporated silicon oxide. This design results in less than 1.5% back-reflection from the oxide into the resist for 10% film thickness variation. Finite-difference time-domain simulations are optimized by comparing higher variable-resolution, more realistic simulations to more efficient, lower variable-resolution simulations. Building on the trilayer stack and optimal simulation specification, simulated exposures of diffraction gratings are analyzed assuming a clipping model of development. Exposures of dense grating patterns with two geometries are performed on trilayer-stack-coated silicon wafers for a range of doses.&lt;/Abstract>
   	&lt;Abstract>(cont.) Transferred grating patterns are analyzed to establish the effect of exposure dose on printed linewidth. A 5% experimental process latitude is achieved at a printed linewidth tolerance of ±15% for the embedded chrome mask exposures and of 25% for the protruding chrome mask exposures. Within the resist, contrast is higher at smaller gratings using the embedded mask.&lt;/Abstract>
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