2026-09-19T03:01:24Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/421192022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Stephen D. Wyatt and Michael H. Perrott.
Kam, Brandon Ray
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2008-09-03T14:38:51Z
2008-09-03T14:38:51Z
2005
2005
http://hdl.handle.net/1721.1/42119
227033826
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 77-79).
This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.
by Brandon Ray Kam.
M.Eng.
79 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
(VDL)² : a jitter measurement built-in self-test circuit for phase locked loops
Jitter measurement built-in self-test circuit for phase locked loops
Thesis
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<Abstract>This paper discusses the development of a new type of BIST circuit, the (VDL)2, with the purpose of measuring jitter in IBM's phase locked loops. The (VDL)2, which stands for Variable Vernier Digital Delay Locked Line, implements both cycle-to-cycle and phase jitter measurements, by using a digital delay locked loop and a 60 stage Vernier delay line. This achieves a nominal jitter resolution of 10 ps with a capture range of +/- 150 ps and does so in real time. The proposed application for this circuit is during manufacturing test of the PLL. The circuit is implemented in IBM's 90 nm process and was completed in the PLL and Clocking Development ASIC group at IBM Microelectronics in Essex Junction, Vermont as part of the VI-A program.</Abstract>
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