2026-09-19T02:28:28Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/430332022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Krste Asanović.
Khan, Asif I. (Asif Imtiaz)
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2008-11-07T18:54:24Z
2008-11-07T18:54:24Z
2008
2008
http://hdl.handle.net/1721.1/43033
243608011
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 49-50).
With the computer hardware industry and the academic world focused on multiprocessor systems, the RAMP project is aiming to provide the infrastructure for supporting high-speed emulation of large scale, massively-parallel multiprocessor systems using FPGAs. The RAMP design framework provides the platform for building this infrastructure. This research utilizes this design framework to emulate various microprocessor memory systems through a model built in an FPGA. We model both the latency and the bandwidth of memory systems through a parameterized emulation platform, thereby, demonstrating the validity of the design framework. We also show the efficiency of the framework through an evaluation of the utilized FPGA resources.
by Asif I. Khan.
S.M.
50 leaves
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Emulation of microprocessor memory systems using the RAMP design framework
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="30928f49-fb25-4b88-9410-b4b7d15e930d">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>Emulation of microprocessor memory systems using the RAMP design framework</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2008</PublicationDate>
<Authors>
<Author>
<DisplayName>Khan, Asif I. (Asif Imtiaz)</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>With the computer hardware industry and the academic world focused on multiprocessor systems, the RAMP project is aiming to provide the infrastructure for supporting high-speed emulation of large scale, massively-parallel multiprocessor systems using FPGAs. The RAMP design framework provides the platform for building this infrastructure. This research utilizes this design framework to emulate various microprocessor memory systems through a model built in an FPGA. We model both the latency and the bandwidth of memory systems through a parameterized emulation platform, thereby, demonstrating the validity of the design framework. We also show the efficiency of the framework through an evaluation of the utilized FPGA resources.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>