2026-09-19T14:43:04Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/430442022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Joel Dawson.
Khanna, Tania
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2008-11-07T18:55:36Z
2008-11-07T18:55:36Z
2008
2008
http://hdl.handle.net/1721.1/43044
243779546
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (leaves 62-64).
In system design, allocation of circuit resources like power and noise budget is a difficult problem. It is difficult to know the optimal distribution of resources because the performance space of each component is not fully characterized. This uncertainty results in an iterative approach with frequent re-design of circuit blocks for different distribution schemes. Equation-based optimization has been shown effective and time efficient in circuit design, but is impractical for systems due to the large number of variables resulting in long solve times. This work shows an equation-based hierarchical optimization strategy suitable for design in deeply scaled CMOS processes. Because it is a hierarchical methodology, it scales gracefully to systems that are much larger than can be handled by known optimization methods. This thesis matches flat and hierarchical optimizations of a 10-stage pipeline ADC in a 0.18-um process. A pipeline ADC was chosen because it is a system small enough to be handled by a flat optimization, yet large enough to be approached with a hierarchical methodology. This allows a quantitative comparison of the computation resources required by each strategy. In this approach, equation-based optimizations generate the Pareto-optimal surfaces of each pipeline stage. Exploiting the surfaces' gentle nature and amenability to low-order equation fits, they are abstracted to higher levels as representations of the circuit block. Thus, resources are allocated at the system level (such as power dissipation, noise budget, gain, etc.) very rapidly and very efficiently using familiar equation-based optimization strategies. In the end we demonstrate an optimization strategy that takes 25x less time to allocate resources than a traditional, flat methodology.
by Tania Khanna.
S.M.
64 leaves
eng
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Equation-based hierarchical optimization of a pipeline ADC
Thesis
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<Abstract>In system design, allocation of circuit resources like power and noise budget is a difficult problem. It is difficult to know the optimal distribution of resources because the performance space of each component is not fully characterized. This uncertainty results in an iterative approach with frequent re-design of circuit blocks for different distribution schemes. Equation-based optimization has been shown effective and time efficient in circuit design, but is impractical for systems due to the large number of variables resulting in long solve times. This work shows an equation-based hierarchical optimization strategy suitable for design in deeply scaled CMOS processes. Because it is a hierarchical methodology, it scales gracefully to systems that are much larger than can be handled by known optimization methods. This thesis matches flat and hierarchical optimizations of a 10-stage pipeline ADC in a 0.18-um process. A pipeline ADC was chosen because it is a system small enough to be handled by a flat optimization, yet large enough to be approached with a hierarchical methodology. This allows a quantitative comparison of the computation resources required by each strategy. In this approach, equation-based optimizations generate the Pareto-optimal surfaces of each pipeline stage. Exploiting the surfaces' gentle nature and amenability to low-order equation fits, they are abstracted to higher levels as representations of the circuit block. Thus, resources are allocated at the system level (such as power dissipation, noise budget, gain, etc.) very rapidly and very efficiently using familiar equation-based optimization strategies. In the end we demonstrate an optimization strategy that takes 25x less time to allocate resources than a traditional, flat methodology.</Abstract>
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