2026-09-19T10:42:16Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/436072022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
James K. Roberge and Edmund J. Balboni.
Santarelli, Keith R. (Keith Robert), 1977-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2008-11-07T20:17:18Z
2008-11-07T20:17:18Z
2000
2000
http://hdl.handle.net/1721.1/43607
46888172
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (leaves 77-78).
It has been found that the amplitude of the 20kHz harmonic at the output of a particular third order [Sigma][Delta] analog to digital converter drifts significantly as the temperature fluctuates. In this document, both methods of ascertaining the source of this drift and ways to reduce it are discussed. First, the settling time of the circuit is explored by analyzing the design of the transmission gates used to implement the switched capacitor integrators in the [Sigma][Delta]. Next, the effects of op amp transistor mismatch is considered via simulations which introduce small random offsets to the widths and lengths in the transistors of each op amp. Finally, a calibration scheme which can be used to eliminate the AC gain variation of the [Sigma][Delta] at 20kHz is analyzed, and simulation results of the circuit used to perform the calibration are portrayed.
by Keith R. Santarelli.
M.Eng.
78 leaves
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A low power digitizer for precision carrier band measurements
Thesis
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<Abstract>It has been found that the amplitude of the 20kHz harmonic at the output of a particular third order [Sigma][Delta] analog to digital converter drifts significantly as the temperature fluctuates. In this document, both methods of ascertaining the source of this drift and ways to reduce it are discussed. First, the settling time of the circuit is explored by analyzing the design of the transmission gates used to implement the switched capacitor integrators in the [Sigma][Delta]. Next, the effects of op amp transistor mismatch is considered via simulations which introduce small random offsets to the widths and lengths in the transistors of each op amp. Finally, a calibration scheme which can be used to eliminate the AC gain variation of the [Sigma][Delta] at 20kHz is analyzed, and simulation results of the circuit used to perform the calibration are portrayed.</Abstract>
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