2026-09-19T14:59:12Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/442932022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Jesús A. del Alamo.
Waldron, Niamh, 1974-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-01-30T16:29:13Z
2009-01-30T16:29:13Z
2007
2007
http://hdl.handle.net/1721.1/44293
272356922
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 123-132).
As CMOS scaling approaches the end of the roadmap it has become a matter of great urgency to explore alternative options to conventional Si devices for logic applications. The high electron mobilities of III-V based compounds makes them an attractive option for use as a channel material. Of these materials, InGaAs offers the best balance between a mature technology and high mobility. InGaAs high electron mobility transistors (HEMTs) have already been shown to hold great promise for logic devices but they are typically not self-aligned nor enhancement mode and as such are not suitable for scaled VLSI applications. In this work a novel self-aligned device architecture for InGaAs HEMT devices is proposed and demonstrated. The key feature of the process is a non-alloyed a W ohmic layer that is separated from the gate by means of an air spacer. The gate to source metal distance is reduced to 60 nm, a 20x improvement over conventional designs where the source to drain distance is typically 1.5 to 2 /Lm. A detailed analysis of the source resistance was carried out and the heterojunction barrier resistance was determined to be the dominant resistance component. Two methods of changing the device threshold voltage are investigated. In the first F is used to passivate Si donors in the insulator layer. In the second the insulator is thinned by means of a dry etch. No degradation of the source resistance was observed using this method, which is an improvement over previous results using wet chemical etching. A 90 nm self-aligned enhancement-mode device with a vertically scaled insulator thickness of 5 nm was fabricated. The device has outstanding logic figures of merit with a VT of 60 mV, g, of 1.3 S/mm, SS of 71 mV/dec, DIBL of 55 mV/V and an I,/Ileak ratio of 2x103.
(cont.) These values are outstanding when compared to state of-the-art Si devices. The relatively low In/Ileak ratio is a consequence of operating a Schottky gate device in enhancement mode. Ultimately a high-k gate dielectric solution will be required.
by Niamh Waldron.
Ph.D.
132 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
InGaAs self-aligned HEMT for logic applications
InGaAs self-aligned high electron mobility transistor for logic applications
Thesis
application/pdf
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="3c34727e-9f13-4d19-8ed7-21397946877c">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>InGaAs self-aligned HEMT for logic applications</Title>
<Subtitle>InGaAs self-aligned high electron mobility transistor for logic applications</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2007</PublicationDate>
<Authors>
<Author>
<DisplayName>Waldron, Niamh, 1974-</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>As CMOS scaling approaches the end of the roadmap it has become a matter of great urgency to explore alternative options to conventional Si devices for logic applications. The high electron mobilities of III-V based compounds makes them an attractive option for use as a channel material. Of these materials, InGaAs offers the best balance between a mature technology and high mobility. InGaAs high electron mobility transistors (HEMTs) have already been shown to hold great promise for logic devices but they are typically not self-aligned nor enhancement mode and as such are not suitable for scaled VLSI applications. In this work a novel self-aligned device architecture for InGaAs HEMT devices is proposed and demonstrated. The key feature of the process is a non-alloyed a W ohmic layer that is separated from the gate by means of an air spacer. The gate to source metal distance is reduced to 60 nm, a 20x improvement over conventional designs where the source to drain distance is typically 1.5 to 2 /Lm. A detailed analysis of the source resistance was carried out and the heterojunction barrier resistance was determined to be the dominant resistance component. Two methods of changing the device threshold voltage are investigated. In the first F is used to passivate Si donors in the insulator layer. In the second the insulator is thinned by means of a dry etch. No degradation of the source resistance was observed using this method, which is an improvement over previous results using wet chemical etching. A 90 nm self-aligned enhancement-mode device with a vertically scaled insulator thickness of 5 nm was fabricated. The device has outstanding logic figures of merit with a VT of 60 mV, g, of 1.3 S/mm, SS of 71 mV/dec, DIBL of 55 mV/V and an I,/Ileak ratio of 2x103.</Abstract>
<Abstract>(cont.) These values are outstanding when compared to state of-the-art Si devices. The relatively low In/Ileak ratio is a consequence of operating a Schottky gate device in enhancement mode. Ultimately a high-k gate dielectric solution will be required.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>