2026-09-19T03:24:47Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/456472022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Matt Rowley and Joel L. Dawson.
Ha, Miranda J. (Miranda Joy)
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-06-25T20:37:54Z
2009-06-25T20:37:54Z
2008
2008
http://hdl.handle.net/1721.1/45647
392223237
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 38).
A low-dropout (LDO) voltage regulator for low-power applications is designed without an external capacitor for compensation. The regulator has two stages, the first a folded cascode amplifier and the second a large pass transistor acting as a common-source amplifier. To better explore the tradeoff between bandwidth and power supply rejection, transistor dimensions are modified to support three different bias current levels for the same topology. Tradeoffs involving phase margin and load capacitance are also explored. In simulation, the regulator provided an output of 1.3 V from an unregulated 1.8 V supply, using a 0.75 V reference. By exploiting the tradeoffs between PSRR, bandwidth, and power consumption, a PSRR between 40-60 dB is achieved with a bandwidth between 10 kHz-350 kHz while burning no more than 150 pA of current. The output voltage is stable for load currents between 18-174 mA.
by Miranda J. Ha.
M.Eng.
38 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A low-power, high-bandwidth LDO voltage regulator with no external capacitor
Low-power, high-bandwidth low-dropout voltage regulator with no external capacitor
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="5a3f1d7e-cb4e-4335-ad2e-3368c659db77">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>A low-power, high-bandwidth LDO voltage regulator with no external capacitor</Title>
<Subtitle>Low-power, high-bandwidth low-dropout voltage regulator with no external capacitor</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2008</PublicationDate>
<Authors>
<Author>
<DisplayName>Ha, Miranda J. (Miranda Joy)</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>A low-dropout (LDO) voltage regulator for low-power applications is designed without an external capacitor for compensation. The regulator has two stages, the first a folded cascode amplifier and the second a large pass transistor acting as a common-source amplifier. To better explore the tradeoff between bandwidth and power supply rejection, transistor dimensions are modified to support three different bias current levels for the same topology. Tradeoffs involving phase margin and load capacitance are also explored. In simulation, the regulator provided an output of 1.3 V from an unregulated 1.8 V supply, using a 0.75 V reference. By exploiting the tradeoffs between PSRR, bandwidth, and power consumption, a PSRR between 40-60 dB is achieved with a bandwidth between 10 kHz-350 kHz while burning no more than 150 pA of current. The output voltage is stable for load currents between 18-174 mA.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>