2026-09-19T07:41:22Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/459982022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Jack Dennis.
Chiou, Albert (Albert C.)
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-06-30T16:57:36Z
2009-06-30T16:57:36Z
2008
2008
http://hdl.handle.net/1721.1/45998
351782388
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 32).
The goal of the "Fresh Breeze Project" is to develop a multi-core chip architecture that supports a better programming model for parallel computing. This architecture combines simultaneous multithreading, a global shared address space, no memory update, and a cycle-free heap to provide a platform for robust, general-purpose, parallel computation. These design choices help simplify classically hard problems such as memory coherency, control flow, and synchronization. An HDL implementation of the core execution unit of a single processing core (many cores are on a single chip) forms the basis of further simulation and synthesis. The design must first be broken down into functional logic blocks and translated into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level "guarded atomic actions" triggered by a rule based system.
by Albert Chiou.
M.Eng.
141 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Design study of a novel computer instruction execution unit
Thesis
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