2026-09-19T03:24:12Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/461662022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Nanju Na and Vladimir Stojanovic.
Kalantarian, Asad
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-06-30T17:35:51Z
2009-06-30T17:35:51Z
2008
2008
http://hdl.handle.net/1721.1/46166
400009371
Includes bibliographical references (p. 75-79).
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Continual increase in high-speed transfer rates is essential in today's world in order to keep up with Moor's law scaling and to meet application demands. This increase in information transfer rates is essentially limited by the bandwidth of the communication channel. Channel loss, signal crosstalk, and power integrity are the important factors affecting the bandwidth of the channel and must be fully understood when designing such high-speed links. Moreover, channel performance optimization requires system level analysis with co-design of different channel components in order to approach the maximum capacity of a channel. In this thesis, we focus on the essential aspects of high-speed channel design with an emphasis on the design of the package area. A technique for reducing discontinuities in the package is introduced, studied, and simulated on IBM package designs to obtain improved package performance. The critical Plated-Through-Hole (PTH) via region at the package and Printed Circuit Board (PCB) interface is also analyzed in a co-study to suggest design rules for overall improved system performance.
by Asad Kalantarian.
M.Eng.
79 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Package and PCB solutions for high-speed data link applications
Package and printed circuit board solutions for high-speed data link applications
Thesis
application/pdf
Publication
unknown
unknown
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<Abstract>Continual increase in high-speed transfer rates is essential in today's world in order to keep up with Moor's law scaling and to meet application demands. This increase in information transfer rates is essentially limited by the bandwidth of the communication channel. Channel loss, signal crosstalk, and power integrity are the important factors affecting the bandwidth of the channel and must be fully understood when designing such high-speed links. Moreover, channel performance optimization requires system level analysis with co-design of different channel components in order to approach the maximum capacity of a channel. In this thesis, we focus on the essential aspects of high-speed channel design with an emphasis on the design of the package area. A technique for reducing discontinuities in the package is introduced, studied, and simulated on IBM package designs to obtain improved package performance. The critical Plated-Through-Hole (PTH) via region at the package and Printed Circuit Board (PCB) interface is also analyzed in a co-study to suggest design rules for overall improved system performance.</Abstract>
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