2026-09-19T03:01:17Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/465342022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Arvind.
Yamhure, Alessandro
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-08-26T16:44:20Z
2009-08-26T16:44:20Z
2008
2008
http://hdl.handle.net/1721.1/46534
416591138
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 52).
This thesis describes the design, construction and integration of a multicore processor and a memory subsystem. The work is part of a joint project with IBM Watson research. The processors have multithreading capacities and implement the PowerPC ISA. The memory system consists of a parameterizable hierarchy of caches and random access memory units. All implementation was done in Bluespec System Verilog hardware synthesis language for placement on FPGA. Furthermore, this document analyzes the main tradeoffs and major challenges involved in building and integrating such a system.
by Alessandro Yamhure.
M.Eng.
52 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
Field-programmable gate array implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
Thesis
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