2026-09-20T03:07:55Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/477172022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Thomas F. Knight, Jr.
Pant, Amrit R. (Amrit Raj), 1971-
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-10-01T15:34:48Z
2009-10-01T15:34:48Z
1998
1998
http://hdl.handle.net/1721.1/47717
42429570
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.
Includes bibliographical references (leaf 71).
SPACERAM is a SIMD architecture optimized for symbolic spatial computations implemented with multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing elements process data coming simultaneously from several memory blocks by applying appropriate shifting and lookup table updates to them. Every processing element contains a permuter which makes it possible to assign data bits from any DRAM block to any functional block within the processing element as specified by controller setup. The lookup table is implemented as a common bus shared by all the processing elements. Micro-architectural analysis of such a processing element presents various possible implementations and trade-off issues associated with them.
by Amrit R. Pant.
M.Eng.
72 leaves
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science
Micro-architectural analysis of SPACERAM processing element
Thesis
application/pdf
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="2ca4f156-f284-4a06-8e70-dce7a17fcfd9">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>Micro-architectural analysis of SPACERAM processing element</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>1998</PublicationDate>
<Authors>
<Author>
<DisplayName>Pant, Amrit R. (Amrit Raj), 1971-</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science</Keyword>
<Abstract>SPACERAM is a SIMD architecture optimized for symbolic spatial computations implemented with multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing elements process data coming simultaneously from several memory blocks by applying appropriate shifting and lookup table updates to them. Every processing element contains a permuter which makes it possible to assign data bits from any DRAM block to any functional block within the processing element as specified by controller setup. The lookup table is implemented as a common bus shared by all the processing elements. Micro-architectural analysis of such a processing element presents various possible implementations and trade-off issues associated with them.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>