2026-09-20T00:13:41Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/477552022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Michael H. Perrott.
Park, Matthew Jeremiah
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2009-10-01T15:38:49Z
2009-10-01T15:38:49Z
2009
2009
http://hdl.handle.net/1721.1/47755
428817944
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
In title on title page, "[Delta]" and "[Epsilon]" appear as upper-case Greek letters.
Includes bibliographical references (p. 135-140).
The use of a VCO-based integrator and quantizer within a continuous-time (CT) [Delta] [Epsilon] analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 [mu]m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADC's, which exclusively made use of the output frequency. Furthermore, the proposed architecture includes a scheme for performing fast dynamic element matching (DEM), enabling first-order shaping of unit-element mismatch in all feedback DAC's.
by Matthew Jeremiah Park.
Ph.D.
140 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A 4th order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantizer
Fourth order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantize
Thesis
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<Abstract>The use of a VCO-based integrator and quantizer within a continuous-time (CT) [Delta] [Epsilon] analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 [mu]m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADC's, which exclusively made use of the output frequency. Furthermore, the proposed architecture includes a scheme for performing fast dynamic element matching (DEM), enabling first-order shaping of unit-element mismatch in all feedback DAC's.</Abstract>
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