2026-09-19T00:37:07Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/531472022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Christopher J. Terman.
Gelb, Benjamin S
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2010-03-25T15:07:04Z
2010-03-25T15:07:04Z
2009
2009
http://hdl.handle.net/1721.1/53147
505532150
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
Includes bibliographical references (leaves 73-74).
The constant desire for increased performance in microprocessor systems has led to the need for specialized hardware cores to accelerate specific computational tasks. In this thesis, we explore the potential of using FPGA partial reconfiguration to create a platform for customized hardware cores that may be loaded on demand, at runtime, and replaced when not in use. We implement two new software tools, bitparse and bitrender, to demonstrate the bitstream relocation technique. Further, we present a functional microprocessor system coupled with a runtime reprogramable peripheral synthesized on a Xilinx Virtex-5 FPGA and discuss its performance implications.
by Benjamin S. Gelb.
M.Eng.
74 leaves
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A timeshared, runtime reconfigurable hardware co-processing architecture
Thesis
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