2026-09-19T17:46:56Zhttps://dspace.mit.edu/server/oai/request

oai:dspace.mit.edu:1721.1/551312022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023

Vladimir Stojanović. Georgas, Michael S. (Michael Stephen) Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2010-05-25T20:51:38Z 2010-05-25T20:51:38Z 2009 2009 http://hdl.handle.net/1721.1/55131 593961602 Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009. Cataloged from PDF version of thesis. Includes bibliographical references (p. 91-92). The throughput bounds of traditional interconnect networks in microprocessors are being pushed to their limits. In past single-core processors, the number of long global wires constituted only a small fraction of the total. However, with the emergence of multi-core systems, where each core must be able to communicate with each other as well as off-chip memory, global interconnects have become a major bottleneck. The solution has been proposed through integrated photonic networks, where multiple channels of information can be placed onto a single low-latency waveguide, reducing the number of interconnects and increasing the speed of transmission. This work presents a novel optical data receiver for integrated optical links. Both the optical receiver and the photodiode are monolithically-integrated in the same CMOS substrate. The highly-digital receiver senses the photodiode current using a regenerative cross-coupled latch. The photodiode is modelled as an ideal current source with a capacitance in parallel. The receiver operates in two phases, receiving one bit per clock cycle, and is able to resolve input photocurrents of less than 50,PA at 5-Gb/s with a power consumption of less than 500yW (100fJ/bit). The receiver was fabricated in a 32-nm CMOS process as part of a flexible test vehicle that will demonstrate various optical components and the electronic systems that interface with them. by Michael S. Georgas. S.M. 92 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. An optical data receiver for integrated photonic interconnects Thesis application/pdf Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="9dc23ac0-6416-4db1-ba3f-9dda68671d32"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>An optical data receiver for integrated photonic interconnects</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2009</PublicationDate> <Authors> <Author> <DisplayName>Georgas, Michael S. (Michael Stephen)</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>The throughput bounds of traditional interconnect networks in microprocessors are being pushed to their limits. In past single-core processors, the number of long global wires constituted only a small fraction of the total. However, with the emergence of multi-core systems, where each core must be able to communicate with each other as well as off-chip memory, global interconnects have become a major bottleneck. The solution has been proposed through integrated photonic networks, where multiple channels of information can be placed onto a single low-latency waveguide, reducing the number of interconnects and increasing the speed of transmission. This work presents a novel optical data receiver for integrated optical links. Both the optical receiver and the photodiode are monolithically-integrated in the same CMOS substrate. The highly-digital receiver senses the photodiode current using a regenerative cross-coupled latch. The photodiode is modelled as an ideal current source with a capacitance in parallel. The receiver operates in two phases, receiving one bit per clock cycle, and is able to resolve input photocurrents of less than 50,PA at 5-Gb/s with a power consumption of less than 500yW (100fJ/bit). The receiver was fabricated in a 32-nm CMOS process as part of a flexible test vehicle that will demonstrate various optical components and the electronic systems that interface with them.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>