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Anantha P. Chandrakasan. Sinangil, Yildiz Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2010-12-06T17:34:51Z 2010-12-06T17:34:51Z 2010 2010 http://hdl.handle.net/1721.1/60183 681911467 Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010. Includes bibliographical references (p. 61-65). Scaling of process technologies has made power management a significant concern for circuit designers. Moreover, denser integration and shrinking geometries also have a negative impact on circuit reliability. Therefore, fault tolerance is becoming a more challenging problem. Static Random Access Memories (SRAMs) play a significant role in circuit power consumption and reliability of digital circuits. This thesis focuses on fault tolerant and low voltage SRAM design. A double error correcting binary BCH codec is chosen to mitigate reliability problems. Different decoding schemes are compared in terms of their synthesized power, area and latency. An alternative decision-tree based decoder is analyzed. This decoder requires 16ns for error correction and 5ns for error detection at 1.2V using 65nm CMOS. Compared to conventional iterative decoding scheme in which error correction takes more than 100 clock cycles for 128-bit word length, the analyzed decoder has a significant latency advantage. Meanwhile, compared to the look-up table (LUT) decoder, the decision-tree based architecture has 2X area and power savings. Hence, the tree-based decoder is an alternative design which does not have the extreme power and area consumption of a LUT decoder and does not have the extreme latency of an iterative implementation. An 8T SRAM block is designed in 65nm CMOS low-power, high VT process for the on-chip caches of a low-voltage processor. This SRAM is designed for the array voltage range of 1.2V to 0.4V. It provides more than 4 orders of magnitude performance scaling and lOX power savings. by Yildiz Sinangil. S.M. 65 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Fault tolerant, low voltage SRAM design Fault tolerant, low voltage Static Random Access Memories design Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="89fd92f4-c1e3-4eb9-91e0-c7c2acf88b02"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Fault tolerant, low voltage SRAM design</Title> <Subtitle>Fault tolerant, low voltage Static Random Access Memories design</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2010</PublicationDate> <Authors> <Author> <DisplayName>Sinangil, Yildiz</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>Scaling of process technologies has made power management a significant concern for circuit designers. Moreover, denser integration and shrinking geometries also have a negative impact on circuit reliability. Therefore, fault tolerance is becoming a more challenging problem. Static Random Access Memories (SRAMs) play a significant role in circuit power consumption and reliability of digital circuits. This thesis focuses on fault tolerant and low voltage SRAM design. A double error correcting binary BCH codec is chosen to mitigate reliability problems. Different decoding schemes are compared in terms of their synthesized power, area and latency. An alternative decision-tree based decoder is analyzed. This decoder requires 16ns for error correction and 5ns for error detection at 1.2V using 65nm CMOS. Compared to conventional iterative decoding scheme in which error correction takes more than 100 clock cycles for 128-bit word length, the analyzed decoder has a significant latency advantage. Meanwhile, compared to the look-up table (LUT) decoder, the decision-tree based architecture has 2X area and power savings. Hence, the tree-based decoder is an alternative design which does not have the extreme power and area consumption of a LUT decoder and does not have the extreme latency of an iterative implementation. An 8T SRAM block is designed in 65nm CMOS low-power, high VT process for the on-chip caches of a low-voltage processor. This SRAM is designed for the array voltage range of 1.2V to 0.4V. It provides more than 4 orders of magnitude performance scaling and lOX power savings.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>