2026-09-18T17:25:39Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/645842022-01-13T07:54:29Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Arvind and Joel Emer.
Pellauer, Michael (Michael Ignatius)
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2011-06-20T15:55:35Z
2011-06-20T15:55:35Z
2011
2011
http://hdl.handle.net/1721.1/64584
727060586
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 159-165).
The goal of this project is to improve computer architecture by accelerating cycle-accurate performance modeling of multicore processors using FPGAs. Contributions include a distributed technique controlling simulation on a highly-parallel substrate, hardware design techniques to reduce development effort, and a specific framework for modeling shared-memory multicore processors paired with realistic On-Chip Networks.
by Michael Pellauer.
Ph.D.
165 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
HAsim : cycle-accurate multicore performance models on FPGAs
Cycle-accurate multicore performance models on FPGAs
Thesis
application/pdf
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="e01864ac-6c06-4cdf-9f90-ad84af21d570">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>HAsim : cycle-accurate multicore performance models on FPGAs</Title>
<Subtitle>Cycle-accurate multicore performance models on FPGAs</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2011</PublicationDate>
<Authors>
<Author>
<DisplayName>Pellauer, Michael (Michael Ignatius)</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>The goal of this project is to improve computer architecture by accelerating cycle-accurate performance modeling of multicore processors using FPGAs. Contributions include a distributed technique controlling simulation on a highly-parallel substrate, hardware design techniques to reduce development effort, and a specific framework for modeling shared-memory multicore processors paired with realistic On-Chip Networks.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>