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Charles G. Sodini and Doris L. Micheva, Nora Iordanova Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2011-10-17T21:26:55Z 2011-10-17T21:26:55Z 2011 http://hdl.handle.net/1721.1/66446 755725319 Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2011. "May 2011." In title on title page, "[mu]" appears as lower case Greek letter. Cataloged from PDF version of thesis. Includes bibliographical references (p. 50-51). As the world continues to do more and more of its signal processing digitally, there is an ever increasing need for high speed high precision signal processors in consumer applications such as digital photography. Technological progress in CMOS fabrication has allowed chips to be made on nano scale processes, but this still comes at a steep price. Especially in chips for which analog components are a priority over digital components, some of the benefits of using nano scale processes diminish, such as smaller area. In these cases, it is worth investigating whether the same performance can be achieved with larger feature size, and therefore, cheaper processes. To that end, a three-stage comparator circuit for use in a digital camera SAR ADC has been ported from its original 65nm process to a 0.11[mu]m process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In 0.11[mu]m the three-stage comparator operates at the same speed, 13% lower RMS noise contributing 0.9 bits difference, and 11% higher power than the original in 65nm. More noteworthy, the 0.11[mu]m latch-only comparator operates at 40% higher speed, equivalent noise, and 72% lower power. by Nora Iordanova Micheva. M.Eng. 51 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="4a59e9da-ffbf-4643-bfa7-7846f8dd2c2b"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2011</PublicationDate> <Authors> <Author> <DisplayName>Micheva, Nora Iordanova</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>As the world continues to do more and more of its signal processing digitally, there is an ever increasing need for high speed high precision signal processors in consumer applications such as digital photography. Technological progress in CMOS fabrication has allowed chips to be made on nano scale processes, but this still comes at a steep price. Especially in chips for which analog components are a priority over digital components, some of the benefits of using nano scale processes diminish, such as smaller area. In these cases, it is worth investigating whether the same performance can be achieved with larger feature size, and therefore, cheaper processes. To that end, a three-stage comparator circuit for use in a digital camera SAR ADC has been ported from its original 65nm process to a 0.11[mu]m process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In 0.11[mu]m the three-stage comparator operates at the same speed, 13% lower RMS noise contributing 0.9 bits difference, and 11% higher power than the original in 65nm. More noteworthy, the 0.11[mu]m latch-only comparator operates at 40% higher speed, equivalent noise, and 72% lower power.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>