2026-09-18T21:12:00Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/697812022-01-13T07:54:36Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Emanuel M. Sachs.
Greenlee, Alison S
Massachusetts Institute of Technology. Dept. of Mechanical Engineering.
Massachusetts Institute of Technology. Department of Mechanical Engineering
2012-03-16T16:02:46Z
2012-03-16T16:02:46Z
2011
2011
http://hdl.handle.net/1721.1/69781
776206613
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 57).
A manufacturing process that produces high quality, inexpensive kerfless silicon wafers for photovoltaic cells is highly desirable. The process herein described was developed to melt and directionally solidify fine-grained silicon wafers at accelerated feed rates for improved electronic properties. The proposed process encapsulates a fine grained silicon wafer which is then sandwiched between two substrates with a specialized release layer. This stack is then zonemelted and recrystallized in a novel zone-melting furnace. The innovations herein described pertain to the design of a novel radiation furnace, the substrate selection, and the process parameters required to repeatedly yields planar wafers, with several centimeter sized grains, and a low dislocation density of10⁴4 cm -² . Specifically, the phenomena that govern the thickness profile of the wafer were examined, and process modifications were made to yield a planar wafer with a +/- 15 tm thickness range over 85% of a 6" wafer. Furthermore, a relationship between the thermal characteristics of the zonemelting furnace, the process feed rate, and the relative grain size were derived. This relationship was used to design and characterize a novel, zone-melting radiation furnace that can solidify a silicon wafer with ~10 solidification angle at 60 mm/min. Additionally, preferential nucleation sites that reduce the likelihood of large grains were identified and experimentally minimized by biasing the wafer to cool preferentially from one side. Finally, mechanisms to create dislocations were identified and minimized. This included minimizing the number of stress concentrations in the wafer and reducing the thermal resistance between the wafer and its supporting conductive substrate.
by Alison S. Greenlee.
S.M.
57 p.
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Mechanical Engineering.
Development of a melting and directional solidification process for improving the grain structure and electronic properties of a silicon wafer
Thesis
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<Abstract>A manufacturing process that produces high quality, inexpensive kerfless silicon wafers for photovoltaic cells is highly desirable. The process herein described was developed to melt and directionally solidify fine-grained silicon wafers at accelerated feed rates for improved electronic properties. The proposed process encapsulates a fine grained silicon wafer which is then sandwiched between two substrates with a specialized release layer. This stack is then zonemelted and recrystallized in a novel zone-melting furnace. The innovations herein described pertain to the design of a novel radiation furnace, the substrate selection, and the process parameters required to repeatedly yields planar wafers, with several centimeter sized grains, and a low dislocation density of10⁴4 cm -² . Specifically, the phenomena that govern the thickness profile of the wafer were examined, and process modifications were made to yield a planar wafer with a +/- 15 tm thickness range over 85% of a 6" wafer. Furthermore, a relationship between the thermal characteristics of the zonemelting furnace, the process feed rate, and the relative grain size were derived. This relationship was used to design and characterize a novel, zone-melting radiation furnace that can solidify a silicon wafer with ~10 solidification angle at 60 mm/min. Additionally, preferential nucleation sites that reduce the likelihood of large grains were identified and experimentally minimized by biasing the wafer to cool preferentially from one side. Finally, mechanisms to create dislocations were identified and minimized. This included minimizing the number of stress concentrations in the wafer and reducing the thermal resistance between the wafer and its supporting conductive substrate.</Abstract>
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