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Li-Shiuan Peh. Chen, Chia-Hsin, Ph. D. Massachusetts Institute of Technology Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2012-05-15T21:12:51Z 2012-05-15T21:12:51Z 2012 2012 http://hdl.handle.net/1721.1/70792 792852030 Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012. Cataloged from PDF version of thesis. Includes bibliographical references (p. 57-60). As CMOS technology improves, the trend of processor designs has gone towards multi-core architectures. Networks-on-Chips (NoCs) have become popular on-chip interconnect fabrics that connect the ever-increasing cores because of their ability to provide high-bandwidth. However, as the number of cores keeps increasing, the endto- end packet latency and the total network power begin to pose tight constraints on NoC designs. In this thesis, we studied architecture proposals designed to tackle this latency and power budget issue. We also studied the impact of applying advanced circuit techniques to these architecture proposals and how to implement these techniques while realizing a NoC design. The thesis begins with an evaluation of physical express topologies and the virtual express topologies that enable the bypassing of intermediate router pipelines. The bypassing of pipeline stages help reduce both end-to-end latency and power consumption since fewer resources are used. We observed that both topologies have similar low-traffic-load latencies and that virtual express topologies result in higher throughput and are more robust across traffic patterns. Physical express topologies, however, deliver a better throughput/watt and can leverage the low-swing link circuits to lower the latency and increase the throughput. Next, then we identified that crossbars, in addition to links, can obtain benefit from the low-swing circuit techniques. We thus developed a layout generation tool for low-swing crossbars and links due to the inability of the existing tools for physical designs to generate these low-swing circuits automatically. The generated crossbars and links using our tool showed 50% energy saving compared to the full-swing synthesized counterpart. We also demonstrated a case study with a router synthesized with the generated crossbar and links. by Chia-Hsin Chen. S.M. 60 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. On-Chip Network exploration and synthesis Networks-on-Chips exploration and synthesis NoCs exploration and synthesis Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="7d68843d-5016-4692-8df4-ab5a590f6693"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>On-Chip Network exploration and synthesis</Title> <Subtitle>Networks-on-Chips exploration and synthesis</Subtitle> <Subtitle>NoCs exploration and synthesis</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2012</PublicationDate> <Authors> <Author> <DisplayName>Chen, Chia-Hsin, Ph. D. Massachusetts Institute of Technology</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>As CMOS technology improves, the trend of processor designs has gone towards multi-core architectures. Networks-on-Chips (NoCs) have become popular on-chip interconnect fabrics that connect the ever-increasing cores because of their ability to provide high-bandwidth. However, as the number of cores keeps increasing, the endto- end packet latency and the total network power begin to pose tight constraints on NoC designs. In this thesis, we studied architecture proposals designed to tackle this latency and power budget issue. We also studied the impact of applying advanced circuit techniques to these architecture proposals and how to implement these techniques while realizing a NoC design. The thesis begins with an evaluation of physical express topologies and the virtual express topologies that enable the bypassing of intermediate router pipelines. The bypassing of pipeline stages help reduce both end-to-end latency and power consumption since fewer resources are used. We observed that both topologies have similar low-traffic-load latencies and that virtual express topologies result in higher throughput and are more robust across traffic patterns. Physical express topologies, however, deliver a better throughput/watt and can leverage the low-swing link circuits to lower the latency and increase the throughput. Next, then we identified that crossbars, in addition to links, can obtain benefit from the low-swing circuit techniques. We thus developed a layout generation tool for low-swing crossbars and links due to the inability of the existing tools for physical designs to generate these low-swing circuits automatically. The generated crossbars and links using our tool showed 50% energy saving compared to the full-swing synthesized counterpart. We also demonstrated a case study with a router synthesized with the generated crossbar and links.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>