2026-09-19T05:22:21Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/784602022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Jesús A. del Alamo.
Guo, Alex
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2013-04-12T19:26:11Z
2013-04-12T19:26:11Z
2012
2012
http://hdl.handle.net/1721.1/78460
834074525
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 65-66).
As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development.
by Alex Guo.
S.M.
66 p.
eng
Massachusetts Institute of Technology
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Nano-scale metal contacts for future III-V CMOS
Nano-scale metal contacts for future III-V complementary metal-oxide-semiconductor
Thesis
application/pdf
Publication
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<Abstract>As modem transistors continue to scale down in size, conventional Si CMOS is reaching its physical limits and alternative technologies are needed to extend Moore's law. Among different candidates, MOSFETs with a III-V compound semiconductor channel are of great interest. Specifically, designs with an InGaAs channel have shown promising results for N type MOSFETs. In a new generation of III-V MOSFETs, one of the key challenges is to shrink device footprint while improving transistor's electrical performance. For future technology nodes, the gate length of MOSFETs needs to shrink below 10 nm, and the source and drain contacts must also decrease to a comparable dimension. A concern about contact scaling is the increase of source resistance. It is predicted that the source resistance will increase exponentially when the contact length is decreased to the nanometer scale regime. In order to understand the issues associated with source contact scaling to the nanometer regime, we have developed a fabrication process for nanometer scale TLM test structures to InGaAs/InAlAs heterostructures for MOSFETs. To analyze these structures, we have also developed a 2D circuit network. After measuring the fabricated devices, the model has been used to extract the relevant electrical parameters that characterize these structures. We have obtained a specific contact resistivity of (0. 116 +/- 0.058) [omega] - um². For Mo/n+-InGaAs contacts, to the best of our knowledge, this is the lowest value reported to date. The fabrication process and the theoretical model presented in this study should help future III-V CMOS scaling research and development.</Abstract>
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