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Charles G. Sodini. Wang, Ching-Chun, 1969- Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2005-08-23T18:21:25Z 2005-08-23T18:21:25Z 2001 2001 http://hdl.handle.net/1721.1/8214 50121258 Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001. Includes bibliographical references (p. 179-183). CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially lower price. The advantages make this technology competent for the next-generation solid-state imaging applications. However, CMOS processes are originally developed for high-performance digital circuits. Fabricating high-quality embedded image sensors with CMOS technologies is not a straightforward task. This motivates the study of CMOS technologies for imaging applications presented in this thesis. The major content of this study can be partitioned into four parts: (a) A two-stage characterization methodology is developed for sensor optimization, including the characterization of large-area photodiodes and comparative analyses on small-dimension sensor arrays with various pixel structures, junction types of the sensors, and other process-related conditions. (b) The mechanism of hot-carrier induced excess minority carriers occurred at the in-pixel transistors is identified and investigated. The influence of the excess carriers on imager performance is analyzed. Suggestions on the pixel design are provided. (c) Signal cross-talk between adjacent pixels is quantified and studied using a sensor array with a specially designed metal shield pattern, which exposes the center pixel and covers the others. The influence of cross-talk on color imager performance is analyzed. Process and layout improvements on cross-talk are also proposed. (d) The trend of pixel size reduction is investigated from the perspective of the achievable optical lens resolution. Using the modulation transfer function (MTF) as an index, optical simulations are performed to examine the relation between the lens resolution and the lens complexity. by Ching-Chun Wang. Ph.D. 196 p. 17002727 bytes 17002483 bytes application/pdf application/pdf eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. A study of CMOS technologies for image sensor applications Study of complementary metal-oxide-silicon technologies for image sensor applications Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="94c7bd9d-5b55-4a38-b4ef-6bf4ae89e4db"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>A study of CMOS technologies for image sensor applications</Title> <Subtitle>Study of complementary metal-oxide-silicon technologies for image sensor applications</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2001</PublicationDate> <Authors> <Author> <DisplayName>Wang, Ching-Chun, 1969-</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>CMOS (Complementary Metal-Oxide-Silicon) imager technology, as compared with mature CCD (Charge-Coupled Device) imager technology, has the advantages of higher circuit integration, lower power consumption, and potentially lower price. The advantages make this technology competent for the next-generation solid-state imaging applications. However, CMOS processes are originally developed for high-performance digital circuits. Fabricating high-quality embedded image sensors with CMOS technologies is not a straightforward task. This motivates the study of CMOS technologies for imaging applications presented in this thesis. The major content of this study can be partitioned into four parts: (a) A two-stage characterization methodology is developed for sensor optimization, including the characterization of large-area photodiodes and comparative analyses on small-dimension sensor arrays with various pixel structures, junction types of the sensors, and other process-related conditions. (b) The mechanism of hot-carrier induced excess minority carriers occurred at the in-pixel transistors is identified and investigated. The influence of the excess carriers on imager performance is analyzed. Suggestions on the pixel design are provided. (c) Signal cross-talk between adjacent pixels is quantified and studied using a sensor array with a specially designed metal shield pattern, which exposes the center pixel and covers the others. The influence of cross-talk on color imager performance is analyzed. Process and layout improvements on cross-talk are also proposed. (d) The trend of pixel size reduction is investigated from the perspective of the achievable optical lens resolution. Using the modulation transfer function (MTF) as an index, optical simulations are performed to examine the relation between the lens resolution and the lens complexity.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>