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Jesús A. del Alamo. Zhao, Xin, Ph. D. Massachusetts Institute of Technology Massachusetts Institute of Technology. Department of Materials Science and Engineering. Massachusetts Institute of Technology. Department of Materials Science and Engineering 2013-11-18T19:14:40Z 2013-11-18T19:14:40Z 2012 2012 http://hdl.handle.net/1721.1/82369 862073786 Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012. Cataloged from PDF version of thesis. Includes bibliographical references (p. 73-78). The non-scalable room temperature 60 mV/dec subthreshold swing of a conventional MOSFET is a fundamental limit to the continuation of transistor power scaling. In order to further reduce transistor power consumption and transistor footprint, new subthreshold transport mechanisms other than thermionic emission over an energy barrier are required. In this thesis, we devote our efforts towards the analysis and demonstration of a superlattice-source nanowire FET which can potentially beat the 60 mV/dec limit. This key to this device concept is to engineer the density of states of electrons at the source via a superlattice. We have calculated the band structure of a superlattice using a self-consistent quantum-mechanical simulation environment. In particular, the effect of transversal confinement on the band structure of a superlattice that occurs in a nanowire has been studied. We show that in order to obtain single-subband conduction, semiconductor nanowires with sub-10 nm diameter have to be fabricated. An analytical expression of the subthreshold swing including the effect of band edges has been derived and good agreement with simulations was achieved. A process flow to fabricate III-V nanowire MOSFETs has been designed. We have developed several key aspects of this process and have demonstrated the capability of fabricating smooth high-aspect ratio sub-10 nm semiconductor pillars in the InGaAs/InAlAs system lattice matched to InP. by Xin Zhao. S.M. 78 p. eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Materials Science and Engineering. Superlattice-source nanowire FET with steep Subthreshold characteristics Superlattice-source nanowire field-effect transistor with steep Subthreshold characteristics Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="f1f52f40-a663-4139-a1a6-49f64b3f1d79"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Superlattice-source nanowire FET with steep Subthreshold characteristics</Title> <Subtitle>Superlattice-source nanowire field-effect transistor with steep Subthreshold characteristics</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2012</PublicationDate> <Authors> <Author> <DisplayName>Zhao, Xin, Ph. D. Massachusetts Institute of Technology</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Materials Science and Engineering.</Keyword> <Abstract>The non-scalable room temperature 60 mV/dec subthreshold swing of a conventional MOSFET is a fundamental limit to the continuation of transistor power scaling. In order to further reduce transistor power consumption and transistor footprint, new subthreshold transport mechanisms other than thermionic emission over an energy barrier are required. In this thesis, we devote our efforts towards the analysis and demonstration of a superlattice-source nanowire FET which can potentially beat the 60 mV/dec limit. This key to this device concept is to engineer the density of states of electrons at the source via a superlattice. We have calculated the band structure of a superlattice using a self-consistent quantum-mechanical simulation environment. In particular, the effect of transversal confinement on the band structure of a superlattice that occurs in a nanowire has been studied. We show that in order to obtain single-subband conduction, semiconductor nanowires with sub-10 nm diameter have to be fabricated. An analytical expression of the subthreshold swing including the effect of band edges has been derived and good agreement with simulations was achieved. A process flow to fabricate III-V nanowire MOSFETs has been designed. We have developed several key aspects of this process and have demonstrated the capability of fabricating smooth high-aspect ratio sub-10 nm semiconductor pillars in the InGaAs/InAlAs system lattice matched to InP.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>