2026-09-19T01:25:06Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/848552022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Anantha P. Chandrakasan.
Zhang, DongNi
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2014-02-10T16:54:58Z
2014-02-10T16:54:58Z
2013
http://hdl.handle.net/1721.1/84855
868311432
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 83-84).
The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries.
by DongNi Zhang.
S.M.
84 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Low-energy radix-2 serial and parallel FFT designs
Low-energy radix-2 serial and parallel Fast Fourier Transform designs
Thesis
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Publication
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<Abstract>The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries.</Abstract>
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