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Judy L. Hoyt. Yu, Tao, Ph. D. Massachusetts Institute of Technology Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2014-02-10T16:55:11Z 2014-02-10T16:55:11Z 2013 http://hdl.handle.net/1721.1/84857 868315152 Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013. Cataloged from PDF version of thesis. Includes bibliographical references (pages 59-62). The supply voltage (VDD) scaling of conventional CMOS technology is approaching its limit due to the physical limit of 60 mV/dec subthreshold swing (SS) at room temperature and the requirement for controlled leakage current. In order to continue VDD scaling for low power applications, novel device structures with steep SS have been proposed. Tunnel-FETs (TFETs) are among the most attractive device structure due to their compatibility with conventional CMOS technology and the potential for outstanding VDD scalability. Heterostructure vertical TFETs with enhanced gate modulation promise significantly improved electrostatic control and drive current relative to lateral tunneling designs. In this thesis, vertical TFETs based on InGaAs/GaAsSb heterostructure are investigated in terms of design, fabrication and electrical characterization. Ino.53Gao.47As/ GaAso.5Sb0.5 heterostructure vertical TFETs are fabricated with an airbridge structure, designed to prevent parasitic tunneling path in the device, with a two-step highly selective undercut process. Electrical measurement of the devices with various gate areas demonstrates area-dependent tunneling current. The Ino.53Gao.47As/ GaAs0 .5 Sb. 5 vertical TFETs with HfO2 high-k gate dielectric (EOT ~ 1.3 nm) exhibit minimum sub-threshold swings of 140 and 58 mV/dec at 300 and 150 K respectively, with an ON-current density of 0.5 [mu]A/[mu]m2 at VDD = 0.5 V at 300 K. A physical model of TFET operation in the ON-state is proposed based on temperature dependent measurements, which reveal a current barrier due to an ungated region near the drain. Simulations illustrate that the gate-to-drain distance must be scaled to eliminate this barrier. In diode-mode operation, outstanding backward diode performance is demonstrated in this system for the first time, with gate-tunable curvature coefficient of 30 V1 near VDS= 0 V. These results indicate the potential of vertical TFETs in hybrid IC applications. by Tao Yu. S.M. 62 pages eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. InGaAs/GaAsSb type-Il heterojunction vertical tunnel-FETs InGaAs/GaAsSb type-2 heterojunction vertical tunnel-FETs InGaAs/GaAsSb type-two heterojunction vertical tunnel-FETs Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="d1eb9521-3fd1-4a26-a31e-6aa9ace1d4be"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>InGaAs/GaAsSb type-Il heterojunction vertical tunnel-FETs</Title> <Subtitle>InGaAs/GaAsSb type-2 heterojunction vertical tunnel-FETs</Subtitle> <Subtitle>InGaAs/GaAsSb type-two heterojunction vertical tunnel-FETs</Subtitle> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2013</PublicationDate> <Authors> <Author> <DisplayName>Yu, Tao, Ph. D. Massachusetts Institute of Technology</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>The supply voltage (VDD) scaling of conventional CMOS technology is approaching its limit due to the physical limit of 60 mV/dec subthreshold swing (SS) at room temperature and the requirement for controlled leakage current. In order to continue VDD scaling for low power applications, novel device structures with steep SS have been proposed. Tunnel-FETs (TFETs) are among the most attractive device structure due to their compatibility with conventional CMOS technology and the potential for outstanding VDD scalability. Heterostructure vertical TFETs with enhanced gate modulation promise significantly improved electrostatic control and drive current relative to lateral tunneling designs. In this thesis, vertical TFETs based on InGaAs/GaAsSb heterostructure are investigated in terms of design, fabrication and electrical characterization. Ino.53Gao.47As/ GaAso.5Sb0.5 heterostructure vertical TFETs are fabricated with an airbridge structure, designed to prevent parasitic tunneling path in the device, with a two-step highly selective undercut process. Electrical measurement of the devices with various gate areas demonstrates area-dependent tunneling current. The Ino.53Gao.47As/ GaAs0 .5 Sb. 5 vertical TFETs with HfO2 high-k gate dielectric (EOT ~ 1.3 nm) exhibit minimum sub-threshold swings of 140 and 58 mV/dec at 300 and 150 K respectively, with an ON-current density of 0.5 [mu]A/[mu]m2 at VDD = 0.5 V at 300 K. A physical model of TFET operation in the ON-state is proposed based on temperature dependent measurements, which reveal a current barrier due to an ungated region near the drain. Simulations illustrate that the gate-to-drain distance must be scaled to eliminate this barrier. In diode-mode operation, outstanding backward diode performance is demonstrated in this system for the first time, with gate-tunable curvature coefficient of 30 V1 near VDS= 0 V. These results indicate the potential of vertical TFETs in hybrid IC applications.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>