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Henry I. Smith. Cheong, Lin Lee Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2014-02-10T16:58:19Z 2014-02-10T16:58:19Z 2013 http://hdl.handle.net/1721.1/84884 868685194 Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013. Cataloged from PDF version of thesis. Includes bibliographical references (pages 169-174). The progress of large-area 2D- and 3D-photonic crystals (PCs) at optical and near infra-red frequencies has been limited by fabrication challenges. Periodic nanostructures must be patterned in high-index and crystalline material such as silicon over large areas (mm² to cm²) with reasonable throughput. These patterns also must be placed coherently over the entire area, and contain controlled defects. No single conventional nanoscale patterning technique is able to fulfil all of these requirements simultaneously. Pattern placement and throughput challenges for planar lithography can be addressed by combining spatial-phase-locked electron-beam lithography (SPLEBL) with lowenergy (sub-2keV) electrons. SPLEBL obtains feedback on the electron-beam position using a reference grid placed on top of the resist. Combining low-energy lithography with SPLEBL places strict requirements on the SPLEBL reference grid. A systematic investigation on a suitable grid material is carried out, and a self-assembled monolayers (SAMs) based grid is fabricated and characterized. Another method of fabricating large area planar PCs is through interference lithography (IL). The key challenge is the inability of IL to pattern defects or non-periodic structures and thermal scanning probe lithography (TSPL) is proposed as a complementary technique to IL. Integrating TSPL with IL requires capability to transfer TSPL-fabricated patterns into underlying material and is challenging due to the thermal-mechanical nature of TSPL. A robust pattern transfer process is designed and the effects of the lithography and etch processes on resolution and line-edge roughness is studied. The membrane-stacking approach, where large-area membranes are fabricated in parallel and then stacked to form a 3D-PC, was proposed as a more efficient method of fabricating 3D-photonic crystals (3D-PCs) compared to conventional fabrication methods. There exists a need to develop techniques capable of fabricating, transferring and assembling these membranes. In this thesis, a membrane-on-carrier (MOC) strategy based on the membrane-stacking approach is proposed. Membranes are fabricated and floated on liquid, and then transferred onto a temporary rigid carrier. The key challenge is in separating the membrane from the rigid carrier onto a receiving substrate. A dissolvable separation layer is introduced between the membrane and carrier, and two membranes are stacked on top of another as proof-of-concept. Finally, azimuthal alignment is incorporated into the process. by Lin Lee Cheong. Ph.D. 174 pages eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Novel advancements in nanofabrication for photonic crystal applications Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="16a8130c-3dda-461d-b625-75da2791598c"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Novel advancements in nanofabrication for photonic crystal applications</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2013</PublicationDate> <Authors> <Author> <DisplayName>Cheong, Lin Lee</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Abstract>The progress of large-area 2D- and 3D-photonic crystals (PCs) at optical and near infra-red frequencies has been limited by fabrication challenges. Periodic nanostructures must be patterned in high-index and crystalline material such as silicon over large areas (mm² to cm²) with reasonable throughput. These patterns also must be placed coherently over the entire area, and contain controlled defects. No single conventional nanoscale patterning technique is able to fulfil all of these requirements simultaneously. Pattern placement and throughput challenges for planar lithography can be addressed by combining spatial-phase-locked electron-beam lithography (SPLEBL) with lowenergy (sub-2keV) electrons. SPLEBL obtains feedback on the electron-beam position using a reference grid placed on top of the resist. Combining low-energy lithography with SPLEBL places strict requirements on the SPLEBL reference grid. A systematic investigation on a suitable grid material is carried out, and a self-assembled monolayers (SAMs) based grid is fabricated and characterized. Another method of fabricating large area planar PCs is through interference lithography (IL). The key challenge is the inability of IL to pattern defects or non-periodic structures and thermal scanning probe lithography (TSPL) is proposed as a complementary technique to IL. Integrating TSPL with IL requires capability to transfer TSPL-fabricated patterns into underlying material and is challenging due to the thermal-mechanical nature of TSPL. A robust pattern transfer process is designed and the effects of the lithography and etch processes on resolution and line-edge roughness is studied. The membrane-stacking approach, where large-area membranes are fabricated in parallel and then stacked to form a 3D-PC, was proposed as a more efficient method of fabricating 3D-photonic crystals (3D-PCs) compared to conventional fabrication methods. There exists a need to develop techniques capable of fabricating, transferring and assembling these membranes. In this thesis, a membrane-on-carrier (MOC) strategy based on the membrane-stacking approach is proposed. Membranes are fabricated and floated on liquid, and then transferred onto a temporary rigid carrier. The key challenge is in separating the membrane from the rigid carrier onto a receiving substrate. A dissolvable separation layer is introduced between the membrane and carrier, and two membranes are stacked on top of another as proof-of-concept. Finally, azimuthal alignment is incorporated into the process.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>