2026-09-19T02:59:42Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/848902022-01-13T07:54:01Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Arvind.
Khan, Asif I. (Asif Imtiaz)
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2014-02-10T16:59:09Z
2014-02-10T16:59:09Z
2013
http://hdl.handle.net/1721.1/84890
868822166
Thesis (Ph. D.)--Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 169-176).
We present a novel modeling methodology which enables the generation of a high-performance, cycle-accurate simulator from a cycle-level specification of the target design. We describe Arete, a full-system multicore processor simulator, developed using our modeling methodology. We provide details on Arete's resource-efficient and high-performance implementation on multiple FPGA platforms, and the architectural experiments performed using it. We present clear evidence that the use of simplified models in architectural studies can lead to wrong conclusions. Through two experiments performed using both cycle-accurate and simplified models, we show that on one hand there are substantial quantitative and qualitative differences in results, and on the other, the results match quite well.
by Asif Imtiaz Khan.
Ph.D.
176 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
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http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Cycle-accurate modeling of multicore processors on FPGAs
Thesis
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