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Lionel C. Kimerling. Reddy, Anand Junuthula, 1973- Massachusetts Institute of Technology. Dept. of Materials Science and Engineering. Massachusetts Institute of Technology. Department of Materials Science and Engineering 2005-08-23T15:09:41Z 2005-08-23T15:09:41Z 2001 2001 http://hdl.handle.net/1721.1/8767 48124358 Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2001. Includes bibliographical references (p. 130-133). The production of future generation integrated circuit devices requires precise control of impurities on the silicon surface. Cleaning of silicon wafers has historically involved the use of concentrated chemicals, large amounts of rinse water, and elevated temperatures to remove particles, metals, and organic matter from the surface. Poor understanding of the mechanisms of contamination has necessitated large margins of error in cleaning processes and has made cleaning the largest consumer of resources in an IC process line. Explosive growth within the semiconductor sector coupled with the increased need for cleaning in device manufacturing presents an enormous burden for the natural environment. By better understanding the relevant parameters in a cleaning step, future process will continue meet performance specifications while simultaneously reducing their impact on the environment. The environmental performance of the manufacturer is limited by the available technologies for wafer cleaning. Design changes occurring at the tool, chemical, and system level all affect the overall environmental impact of a fab . A modified Cost of Ownership (CoO) expression based on the tool consumable cost (CC), footprint (F), yield (Y), throughput (T), and utilization (U) is presented as a guideline for identifying the next generation of 'green' technologies. Barriers to the implementation of an ideal wetbench are also discussed. The intrinsic silicon-HF interface provides a baseline for understanding the impact of contamination on the electronic quality of the surface. Minority carrier lifetime measurements made by Radio-Frequency Photoconductance Decay (RF-PCD) show that defects on this surface are not described by any known models for a single mid-gap, electronic state. A model is presented in which each physical defect introduces two coupled mid-gap states. By analogy with Pb-centers observed at the Si-Si02 interface, these states correspond to the three physical states of a dangling bond. The doublyoccupied state may play a role in native oxide growth and metal deposition; the unoccupied state is a likely site for attack during fluoride etching. Metal contaminants at the silicon-liquid interface have also been studied using RF-PCD. The deposition of part per trillion (ppt) levels of Cu is shown to increase by a factor of 17 .5 by using a 500: 1 solution of HF instead of a 100: 1 solution. This strong dependence arises from a shift in the electrochemical potential at the wafer surf ace. With the reduction in [Ir], the potential shifts to more cathodic values and causes the Cu deposition rate to increase. To prevent unacceptable levels of contamination from dilute HF solutions, the purity of a D:l HF bath must scale as D-1.78. by Anand Junuthula Reddy. Ph.D. 133 p. 8577287 bytes 8577046 bytes application/pdf application/pdf eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Materials Science and Engineering. Design principles for high performance, low environmental impact silicon cleans Thesis application/pdf Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="9628ddfc-4035-4c10-aa1b-fc999b653ecb"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Design principles for high performance, low environmental impact silicon cleans</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2001</PublicationDate> <Authors> <Author> <DisplayName>Reddy, Anand Junuthula, 1973-</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Materials Science and Engineering.</Keyword> <Abstract>The production of future generation integrated circuit devices requires precise control of impurities on the silicon surface. Cleaning of silicon wafers has historically involved the use of concentrated chemicals, large amounts of rinse water, and elevated temperatures to remove particles, metals, and organic matter from the surface. Poor understanding of the mechanisms of contamination has necessitated large margins of error in cleaning processes and has made cleaning the largest consumer of resources in an IC process line. Explosive growth within the semiconductor sector coupled with the increased need for cleaning in device manufacturing presents an enormous burden for the natural environment. By better understanding the relevant parameters in a cleaning step, future process will continue meet performance specifications while simultaneously reducing their impact on the environment. The environmental performance of the manufacturer is limited by the available technologies for wafer cleaning. Design changes occurring at the tool, chemical, and system level all affect the overall environmental impact of a fab . A modified Cost of Ownership (CoO) expression based on the tool consumable cost (CC), footprint (F), yield (Y), throughput (T), and utilization (U) is presented as a guideline for identifying the next generation of &apos;green&apos; technologies. Barriers to the implementation of an ideal wetbench are also discussed. The intrinsic silicon-HF interface provides a baseline for understanding the impact of contamination on the electronic quality of the surface. Minority carrier lifetime measurements made by Radio-Frequency Photoconductance Decay (RF-PCD) show that defects on this surface are not described by any known models for a single mid-gap, electronic state. A model is presented in which each physical defect introduces two coupled mid-gap states. By analogy with Pb-centers observed at the Si-Si02 interface, these states correspond to the three physical states of a dangling bond. The doublyoccupied state may play a role in native oxide growth and metal deposition; the unoccupied state is a likely site for attack during fluoride etching. Metal contaminants at the silicon-liquid interface have also been studied using RF-PCD. The deposition of part per trillion (ppt) levels of Cu is shown to increase by a factor of 17 .5 by using a 500: 1 solution of HF instead of a 100: 1 solution. This strong dependence arises from a shift in the electrochemical potential at the wafer surf ace. With the reduction in [Ir], the potential shifts to more cathodic values and causes the Cu deposition rate to increase. To prevent unacceptable levels of contamination from dilute HF solutions, the purity of a D:l HF bath must scale as D-1.78.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>