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Akintunde Ibitayo (Tayo) Akinwande. Pflug, David George Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science 2005-08-23T15:28:14Z 2005-08-23T15:28:14Z 2000 2000 http://hdl.handle.net/1721.1/8804 48245126 Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. Includes bibliographical references (p. 215-223). by David George Pflug. Ph.D. 223 p. 21719832 bytes 21719592 bytes application/pdf application/pdf eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Electrical Engineering and Computer Science. Low voltage field emitter arrays through aperture scaling Thesis Field-emission arrays (FEAs) are under consideration for a variety of electronic device applications. The reduction of device turn-on and operating voltages has been a topic of intense FEA research. The purpose of this work was to explore the reduction of FEA operating voltage through scaling the gate aperture and the tip radius, with the ultimate objective of integrating FEAs with CMOS technology. This work will also examine the suitability of "classical" electron emission theories when dimensions are scaled. We report the results of experimental and numerical simulation studies of the scaling of field emitter array (FEA) gate apertures to 100 nm and below. Electrostatic simulation indicates that by scaling the gate aperture, it is possible to fabricate devices that will support flat panel display applications at a gate voltage of 15 V. We demonstrated 100-nm-gate aperture molybdenum FEAs that turned on at gate voltages as low as 12 V and achieved a current density of 10 [mu]A/cm2 at 17 V. It was possible to modulate the emission current density of the molybdenum devices by three orders of magnitude with a gate voltage swing of 5 V. The concept of device scaling was then applied to a silicon system where ultra small field emitters were fabricated, using oxidation sharpening, at a 200 nm period with gate apertures as small as 70 nm. We demonstrated 70-nm-gate aperture silicon FEAs that turned on at gate voltages as low as 10 V and achieved emission currents of 1 pA at Vg of 13 V which represents an array current density of approximately 10,000 [mu]A/cm 2. Currents as high as 30 gA were measured at Vg of 21 V. Transmission electron microscopy (TEM) of the tips verified that the tip radii have a lognormal distribution with a mean radius of 4.5 nm. The measured tip radii are consistent with the electrical characterization of the devices. application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="ab32f938-c284-44d2-8f85-a8c4320e52c2"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Low voltage field emitter arrays through aperture scaling</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2000</PublicationDate> <Authors> <Author> <DisplayName>Pflug, David George</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>