2026-09-19T10:45:54Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/900002026-06-16T18:53:11Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Anantha P. Chandrakasan.
Rithe, Rahul (Rahulkumar Jagdish)
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2014-09-19T21:33:35Z
2014-09-19T21:33:35Z
2014
2014
http://hdl.handle.net/1721.1/90000
890132465
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages [189]-203).
Portable electronics has fueled the rich emergence of multimedia applications that have led to the exponential growth in content creation and consumption. New energy-efficient integrated circuits and systems are necessary to enable the increasingly complex augmented-reality applications, such as high-performance multimedia, "big-data" processing and smart healthcare, in real-time on mobile platforms of the future. This thesis presents an energy-efficient system design approach with algorithm, architecture and circuit co-design for multiple application areas. A shared transform engine, capable of supporting multiple video coding standards in real-time with ultra-low power consumption, is developed. The transform engine, implemented using 45 nm CMOS technology, supports Quad Full-HD (4k x 2k) video coding with reconfigurable processing for H.264 and VC-1 standards at 0.5 V and operates down to 0.3 V to maximize energy-efficiency. Algorithmic and architectural optimizations, including matrix factorization, transpose memory elimination and data dependent processing, achieve significant savings in area and power consumption. A reconfigurable processor for computational photography is presented. An efficient implementation of the 3D bilateral grid structure supports a wide range of non-linear filtering applications, including high dynamic range imaging, low-light enhancement and glare reduction. The processor, implemented using 40 nm CMOS technology, enables real-time processing of HD images, while operating down to 0.5 V and achieving 280x higher energy-efficiency compared to software implementations on state-of-the-art mobile processors. A scalable architecture enables 8x energy scalability for the same throughput performance, while trading-off output resolution for energy. Widespread use of medical imaging techniques has been limited by factors such as size, weight, cost and complex user interface. A portable medical imaging platform for accurate objective quantification of skin condition progression, using robust computer vision techniques, is presented. Clinical validation shows 95% accuracy in progression assessment. Algorithmic optimizations, reducing the memory bandwidth and computational complexity by over 80%, pave the way for energy-efficient hardware implementation to enable real-time portable medical imaging.
by Rahul Rithe.
Ph.D.
203 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Energy-efficient system design for mobile processing platforms
Thesis
application/pdf
Publication
unknown
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<Abstract>Portable electronics has fueled the rich emergence of multimedia applications that have led to the exponential growth in content creation and consumption. New energy-efficient integrated circuits and systems are necessary to enable the increasingly complex augmented-reality applications, such as high-performance multimedia, "big-data" processing and smart healthcare, in real-time on mobile platforms of the future. This thesis presents an energy-efficient system design approach with algorithm, architecture and circuit co-design for multiple application areas. A shared transform engine, capable of supporting multiple video coding standards in real-time with ultra-low power consumption, is developed. The transform engine, implemented using 45 nm CMOS technology, supports Quad Full-HD (4k x 2k) video coding with reconfigurable processing for H.264 and VC-1 standards at 0.5 V and operates down to 0.3 V to maximize energy-efficiency. Algorithmic and architectural optimizations, including matrix factorization, transpose memory elimination and data dependent processing, achieve significant savings in area and power consumption. A reconfigurable processor for computational photography is presented. An efficient implementation of the 3D bilateral grid structure supports a wide range of non-linear filtering applications, including high dynamic range imaging, low-light enhancement and glare reduction. The processor, implemented using 40 nm CMOS technology, enables real-time processing of HD images, while operating down to 0.5 V and achieving 280x higher energy-efficiency compared to software implementations on state-of-the-art mobile processors. A scalable architecture enables 8x energy scalability for the same throughput performance, while trading-off output resolution for energy. Widespread use of medical imaging techniques has been limited by factors such as size, weight, cost and complex user interface. A portable medical imaging platform for accurate objective quantification of skin condition progression, using robust computer vision techniques, is presented. Clinical validation shows 95% accuracy in progression assessment. Algorithmic optimizations, reducing the memory bandwidth and computational complexity by over 80%, pave the way for energy-efficient hardware implementation to enable real-time portable medical imaging.</Abstract>
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