2026-09-19T05:27:57Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/916962026-06-06T00:55:55Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Jesus del Alamo and Craig Easson.
Mandal, Anartya
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2014-11-24T16:16:14Z
2014-11-24T16:16:14Z
2014
2014
http://hdl.handle.net/1721.1/91696
894247793
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis. In title on title page, "[m̳u̳]" appear as lower case Greek letter.
Includes bibliographical references (page 71).
A highly accelerated lifetime test (HALT), is a stress testing methodology for accelerating product reliability that is universally conducted during the engineering development process. In conducting a HALT for circuit components, a burn-in procedure is executed, where the circuit/device is heated to a high temperature for a number of days until finally cooled back to room temperature in order for voltage, current or parameter variations to be compared. When such changes to voltage, cur- rent, or parameters are permanent, no amount of further burn-ins, cool downs or temperature cycling can return the parameter of interest back to its original value it held prior to the burn-in. This is called lifetime-drift and is a problem that circuit simulators do not model. The inability to simulate life-time drift leads to production delays, increasing costs and decreased reliability. In this thesis, I investigated the physics, created a circuit simulation model and implemented an easy-to-use utility for detecting and measuring lifetime drift in 0.18m BiCMOS high sheet resistance (RPH) polysilicon resistors. The circuit model was made using Cadence-Spectre and Verilog-A. The lifetime drift utility was written using Ocean scripting language.
by Anartya Mandal.
M.Eng.
71 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Modeling 0.18[m̳u̳]m BiCMOS (S18) high sheet resistance (RPH) polysilicon resistor lifetime drift
Thesis
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<Abstract>A highly accelerated lifetime test (HALT), is a stress testing methodology for accelerating product reliability that is universally conducted during the engineering development process. In conducting a HALT for circuit components, a burn-in procedure is executed, where the circuit/device is heated to a high temperature for a number of days until finally cooled back to room temperature in order for voltage, current or parameter variations to be compared. When such changes to voltage, cur- rent, or parameters are permanent, no amount of further burn-ins, cool downs or temperature cycling can return the parameter of interest back to its original value it held prior to the burn-in. This is called lifetime-drift and is a problem that circuit simulators do not model. The inability to simulate life-time drift leads to production delays, increasing costs and decreased reliability. In this thesis, I investigated the physics, created a circuit simulation model and implemented an easy-to-use utility for detecting and measuring lifetime drift in 0.18m BiCMOS high sheet resistance (RPH) polysilicon resistors. The circuit model was made using Cadence-Spectre and Verilog-A. The lifetime drift utility was written using Ocean scripting language.</Abstract>
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