2026-09-19T17:50:52Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/916982026-06-06T00:48:53Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Stefano D' Aquino and Charles G. Sodini.
Poitzsch, Alec Julius
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2014-11-24T16:16:22Z
2014-11-24T16:16:22Z
2014
2014
http://hdl.handle.net/1721.1/91698
894353395
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 173-174).
This project details the design and evaluation of an operational amplifier designed in XF40, a 40 Volt bipolar process. Initially the signal path circuitry of the amplifier is outlined. Design decisions are chiefly formed around high voltage and high current drive functionality. A novel topology is introduced which compensates base current errors introduced by the individual stages, resulting in a very low (first-order canceled) overall input-referred voltage offset. Novel features are introduced which expand the functionality of the amplifier. Input stage gm is configurable, allowing for the tuning of amplifier bandwidth for a given gain configuration. A robust current-limiting architecture is implemented which allows for a user-configurable output current limit. When this current limit is reached, the amplifier latches into an alternate mode of operation, protecting the amplifier and the load. We utilize disjoint voltage supply rails at the input and output of the amplifier, substantially minimizing overall power dissipation. The chosen topology permits this feature without the introduction of additional errors. We introduce a "boosting" circuit which extends the large signal bandwidth and slew rate of the amplifier. Amplifier performance is evaluated through simulation in Cadence and ADICE (SPICE). The amplifier is capable of driving 1 Ampere through capacitive and resistive loads. The result is a low distortion amplifier with microvolt-order input-referred offset (VOS), 65 MHz large signal bandwidth, and 3000 V/[mu]s slew rate, powered at 20 mA quiescent current.
by Alec Julius Poitzsch.
M.Eng.
174 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A high voltage, high current, low error operational amplifier with novel features
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="19f83585-f4c2-4e91-8ac2-427f35c6d79f">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>A high voltage, high current, low error operational amplifier with novel features</Title>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2014</PublicationDate>
<Authors>
<Author>
<DisplayName>Poitzsch, Alec Julius</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>This project details the design and evaluation of an operational amplifier designed in XF40, a 40 Volt bipolar process. Initially the signal path circuitry of the amplifier is outlined. Design decisions are chiefly formed around high voltage and high current drive functionality. A novel topology is introduced which compensates base current errors introduced by the individual stages, resulting in a very low (first-order canceled) overall input-referred voltage offset. Novel features are introduced which expand the functionality of the amplifier. Input stage gm is configurable, allowing for the tuning of amplifier bandwidth for a given gain configuration. A robust current-limiting architecture is implemented which allows for a user-configurable output current limit. When this current limit is reached, the amplifier latches into an alternate mode of operation, protecting the amplifier and the load. We utilize disjoint voltage supply rails at the input and output of the amplifier, substantially minimizing overall power dissipation. The chosen topology permits this feature without the introduction of additional errors. We introduce a "boosting" circuit which extends the large signal bandwidth and slew rate of the amplifier. Amplifier performance is evaluated through simulation in Cadence and ADICE (SPICE). The amplifier is capable of driving 1 Ampere through capacitive and resistive loads. The result is a low distortion amplifier with microvolt-order input-referred offset (VOS), 65 MHz large signal bandwidth, and 3000 V/[mu]s slew rate, powered at 20 mA quiescent current.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>