2026-09-18T19:34:35Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/917002026-06-06T00:55:26Zcom_1721.1_7582com_1721.1_7581col_1721.1_131023
Charles G. Sodini and Matthew L. Courcy.
Tran, Ky-Anh
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2014-11-24T16:16:29Z
2014-11-24T16:16:29Z
2014
2014
http://hdl.handle.net/1721.1/91700
894491174
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 123-125).
The spurious-free dynamic range of RF DAC's are limited by the heavy digital do- main switching, which interferes with the analog output signal. A design, layout and simulation of a spread-spectrum clock generator (SSCG) is presented. The SSCG modulates the clock frequency used to switch the digital blocks of the DAC in order to reduce electromagnetic interference (EMI) spurs at the analog output signal of the DAC. Leveraging on a phase control architecture rather than a traditional PLL, the SSCG system is shown to reduce the spectral height a divided down clock spur up to 19.6dB. The SSCG is designed in TSMC's 65nm CMOS process. It takes in quadrature, differential clocks at either 2.5GHz or 5GHz, and provides quadrature output clocks at 625MHz or 1.25GHz. The output spectrum of the clock can be attenuated up to 19.6dB relative to the spectrum of an unspread clock. The core of the SSCG is a phase interpolator, which takes in quadrature input clocks and interpolates between them to move the frequency around. To help process the signals before and after interpolation, the SSCG incorporates input variable gain lters, output restoration buffers and divide by 4 circuits. Extensive transistor and behavioral simulations are used to verify the design.
by Ky-Anh Tran.
M.Eng.
125 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
A spread-spectrum clock generator using phase interpolation for EMI reduction
Thesis
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<Abstract>The spurious-free dynamic range of RF DAC's are limited by the heavy digital do- main switching, which interferes with the analog output signal. A design, layout and simulation of a spread-spectrum clock generator (SSCG) is presented. The SSCG modulates the clock frequency used to switch the digital blocks of the DAC in order to reduce electromagnetic interference (EMI) spurs at the analog output signal of the DAC. Leveraging on a phase control architecture rather than a traditional PLL, the SSCG system is shown to reduce the spectral height a divided down clock spur up to 19.6dB. The SSCG is designed in TSMC's 65nm CMOS process. It takes in quadrature, differential clocks at either 2.5GHz or 5GHz, and provides quadrature output clocks at 625MHz or 1.25GHz. The output spectrum of the clock can be attenuated up to 19.6dB relative to the spectrum of an unspread clock. The core of the SSCG is a phase interpolator, which takes in quadrature input clocks and interpolates between them to move the frequency around. To help process the signals before and after interpolation, the SSCG incorporates input variable gain lters, output restoration buffers and divide by 4 circuits. Extensive transistor and behavioral simulations are used to verify the design.</Abstract>
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