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Stephen C. Graves. Bhadauria, Anubha Singh Massachusetts Institute of Technology. Department of Mechanical Engineering. Massachusetts Institute of Technology. Department of Mechanical Engineering 2015-02-05T18:28:03Z 2015-02-05T18:28:03Z 2014 2014 http://hdl.handle.net/1721.1/93841 900968103 Thesis: M. Eng. in Manufacturing, Massachusetts Institute of Technology, Department of Mechanical Engineering, 2014. Cataloged from PDF version of thesis. Includes bibliographical references (page 63). Processes at a semiconductor equipment manufacturing facility were studied with the goal to reduce the production lead time. Based on the principles of lean manufacturing, DMAIC methodology was used to guide the process. Value Stream Mapping (VSM) of the whole process was done to determine that the Universal End Station (UES) was the module with the longest lead time. This work focuses on the optimization of the testing process on the UES. Time studies were conducted for the assembly and test of the UES module and analysis of results revealed a testing process that is serial and thus of a very long duration. Further investigations revealed that some of the processes required the test technician to do manual calibrations and measurements which resulted in long test times. Based on the interviews with involved personnel, historical data analysis and the research carried out, specific tests were recommended for automated testing and parallel testing. A decision tree was developed to help aid in the selection of the suitable candidates for automation while a dependency network diagram was developed to aid in selection of candidates for parallel testing. It is projected that these recommendations will reduce the Testing lead time of UES by 8.4% and labor hours by 16.3%. Keywords: Lean manufacturing, semiconductor, optimization, bottle neck, lead time, DMAIC, Value Stream Mapping, Time study, Root cause analysis. by Anubha Singh Bhadauria. M.Eng. in Manufacturing 63 pages eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Mechanical Engineering. Production lead time reduction in a semiconductor capital equipment manufacturing plant through optimized testing protocols Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="3f42fa14-c2a2-4024-b95c-e7e077a2cdff"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Production lead time reduction in a semiconductor capital equipment manufacturing plant through optimized testing protocols</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2014</PublicationDate> <Authors> <Author> <DisplayName>Bhadauria, Anubha Singh</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Mechanical Engineering.</Keyword> <Abstract>Processes at a semiconductor equipment manufacturing facility were studied with the goal to reduce the production lead time. Based on the principles of lean manufacturing, DMAIC methodology was used to guide the process. Value Stream Mapping (VSM) of the whole process was done to determine that the Universal End Station (UES) was the module with the longest lead time. This work focuses on the optimization of the testing process on the UES. Time studies were conducted for the assembly and test of the UES module and analysis of results revealed a testing process that is serial and thus of a very long duration. Further investigations revealed that some of the processes required the test technician to do manual calibrations and measurements which resulted in long test times. Based on the interviews with involved personnel, historical data analysis and the research carried out, specific tests were recommended for automated testing and parallel testing. A decision tree was developed to help aid in the selection of the suitable candidates for automation while a dependency network diagram was developed to aid in selection of candidates for parallel testing. It is projected that these recommendations will reduce the Testing lead time of UES by 8.4% and labor hours by 16.3%. Keywords: Lean manufacturing, semiconductor, optimization, bottle neck, lead time, DMAIC, Value Stream Mapping, Time study, Root cause analysis.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>