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Roy Welsch and Duane Boning. Teh, Weng Hong Leaders for Global Operations Program. Leaders for Global Operations Program at MIT Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science Sloan School of Management 2015-09-29T18:59:43Z 2015-09-29T18:59:43Z 2014 2014 http://hdl.handle.net/1721.1/99040 921432746 Thesis: M.B.A., Massachusetts Institute of Technology, Sloan School of Management, 2014. In conjunction with the Leaders for Global Operations Program at MIT. Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014. In conjunction with the Leaders for Global Operations Program at MIT. Cataloged from PDF version of thesis. Includes bibliographical references (pages 191-197). This dissertation presents original work in the development of multi-strata subsurface infrared (1.342 [mu]m) nanosecond pulsed laser die singulation (stealth dicing) to enable defect-free ultra-thin stacked memory dies. The over-arching contribution is the first comprehensive and systematic experimental study of stealth dicing, encompassing process physics and simulation, characterization, optimization, and integration, as well as operations management, including statistical process control, sensitivities, interactions, and risk analysis. This work exploits the multi-strata interactions between generated thermal shockwaves and the preceding dislocation layers formed to initiate controlled crack fractures that separate the individual dies from within the interior of the wafer as a method for significant singulation-related defect reduction and die strength enhancement. A new partial-stealth dicing before grinding (p-SDBG) integration based upon the tandem use of three-strata stealth dicing followed by static loading from backgrinding to complete full kerf separation has successfully demonstrated defect-free eight die stacks of 25 and 46 [mu]m thick 2D NAND memory dies on high backside reflectance wafers for the first time. This work resulted in a 3.5% mean increase in memory/system test yield and has been used to realize production-worthy 64 GB retail memory products after passing reliability tests. Based on unit loadings at SanDisk Shanghai for 2014, this translates to annual cost savings averaging $12.OM when extending this technology to all systems-in-package (SIP) products consisting of 4-, 8-, and 16-die stacks. by Weng Hong Teh. M.B.A. S.M. 203 pages eng Massachusetts Institute of Technology M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582 Sloan School of Management. Electrical Engineering and Computer Science. Leaders for Global Operations Program. Stealth dicing characterization, optimization, integration, and operations management for ultra-thin stacked memory dies Thesis application/pdf false Publication unknown unknown <Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="293cc17d-7284-4645-927b-0dbb2a028677"> <Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type> <Language>eng</Language> <Title>Stealth dicing characterization, optimization, integration, and operations management for ultra-thin stacked memory dies</Title> <PublishedIn> <Publication> </Publication> </PublishedIn> <PublicationDate>2014</PublicationDate> <Authors> <Author> <DisplayName>Teh, Weng Hong</DisplayName> <Affiliation> <OrgUnit> </OrgUnit> </Affiliation> </Author> </Authors> <Editors> </Editors> <Publishers> <Publisher> <DisplayName>Massachusetts Institute of Technology</DisplayName> <OrgUnit /> </Publisher> </Publishers> <License>http://dspace.mit.edu/handle/1721.1/7582</License> <Keyword>Sloan School of Management.</Keyword> <Keyword>Electrical Engineering and Computer Science.</Keyword> <Keyword>Leaders for Global Operations Program.</Keyword> <Abstract>This dissertation presents original work in the development of multi-strata subsurface infrared (1.342 [mu]m) nanosecond pulsed laser die singulation (stealth dicing) to enable defect-free ultra-thin stacked memory dies. The over-arching contribution is the first comprehensive and systematic experimental study of stealth dicing, encompassing process physics and simulation, characterization, optimization, and integration, as well as operations management, including statistical process control, sensitivities, interactions, and risk analysis. This work exploits the multi-strata interactions between generated thermal shockwaves and the preceding dislocation layers formed to initiate controlled crack fractures that separate the individual dies from within the interior of the wafer as a method for significant singulation-related defect reduction and die strength enhancement. A new partial-stealth dicing before grinding (p-SDBG) integration based upon the tandem use of three-strata stealth dicing followed by static loading from backgrinding to complete full kerf separation has successfully demonstrated defect-free eight die stacks of 25 and 46 [mu]m thick 2D NAND memory dies on high backside reflectance wafers for the first time. This work resulted in a 3.5% mean increase in memory/system test yield and has been used to realize production-worthy 64 GB retail memory products after passing reliability tests. Based on unit loadings at SanDisk Shanghai for 2014, this translates to annual cost savings averaging $12.OM when extending this technology to all systems-in-package (SIP) products consisting of 4-, 8-, and 16-die stacks.</Abstract> <Access xmlns="http://purl.org/coar/access_right" > </Access> </Publication>