2026-09-19T17:49:32Zhttps://dspace.mit.edu/server/oai/requestoai:dspace.mit.edu:1721.1/997842026-06-17T14:46:02Zcom_1721.1_7582com_1721.1_7581col_1721.1_131022
Vladimir Stojanovié.
Sun, Chen, Ph. D. Massachusetts Institute of Technology
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
2015-11-09T19:12:57Z
2015-11-09T19:12:57Z
2015
2015
http://hdl.handle.net/1721.1/99784
927437793
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 173-183).
As raw compute power of a single chip continues to scale into the multi-teraflop regime, the processor I/O communication fabric must scale proportionally in order to prevent a performance bottleneck. As electrical wires suffer from high channel losses, pin-count constraints, and crosstalk, they are projected to fall short of the demands required by future memory systems. Silicon-photonic optical links overcome the fundamental tradeoffs of electrical wires; dense wavelength division multiplexing (DWDM) - where multiple data channels share a single waveguide or fiber to greatly extend bandwidth density - and the potential to combine at chip-scale with a very large scale integrated (VLSI) CMOS electrical chip make them a promising alternative for next-generation processor I/O. The key device for VLSI photonics is the optical microring resonator, a compact micrometer-scale device enabling energy-efficient modulation, DWDM channel selection, and sometimes even photo-detection. While these advantages have generated considerable interest in silicon-photonics, present-day integration efforts have been limited in scale owing to the difficulty of integration with advanced electronics and the sensitivity of microring resonators to both process and thermal variations. This thesis develops and demonstrates the pieces of a photonically-interconnected processor-to-memory system. We demonstrate a complete optical transceiver platform in a commercial 45 nm SOI process, showing that optical devices can be integrated into an advanced, commercial CMOS SOI process even without any changes to the manufacturing steps of the native process. To show that photonic interconnects are viable even for commoditized and cost-sensitive memory, we develop the first monolithic electronic-photonic links in bulk CMOS. As the stabilization of ring resonators is critical for use in VLSI systems, we contribute to the understanding of process and thermal variations on microring resonators, leading to the demonstration of a complete auto-locking microring tuning system that is agnostic to the transmitted data sequence and suitable for unencoded low-latency processor-to-memory traffic. Finally, the technology and methods developed in this work culminate in the demonstration of the world's first processor chip with integrated photonic interconnects, which uses monolithically integrated photonic devices to optically communicate to main memory.
by Chen Sun.
Ph.D.
183 pages
eng
Massachusetts Institute of Technology
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
http://dspace.mit.edu/handle/1721.1/7582
Electrical Engineering and Computer Science.
Silicon-photonics for VLSI systems
Silicon-photonics for very large scale integrated systems
Thesis
application/pdf
false
Publication
unknown
unknown
<Publication xmlns="https://www.openaire.eu/cerif-profile/1.1/" id="b52041c4-563b-481b-9d08-3f8b6a4615c0">
<Type xmlns="https://www.openaire.eu/cerif-profile/vocab/COAR_Publication_Types">http://purl.org/coar/resource_type/c_1843</Type>
<Language>eng</Language>
<Title>Silicon-photonics for VLSI systems</Title>
<Subtitle>Silicon-photonics for very large scale integrated systems</Subtitle>
<PublishedIn>
<Publication>
</Publication>
</PublishedIn>
<PublicationDate>2015</PublicationDate>
<Authors>
<Author>
<DisplayName>Sun, Chen, Ph. D. Massachusetts Institute of Technology</DisplayName>
<Affiliation>
<OrgUnit>
</OrgUnit>
</Affiliation>
</Author>
</Authors>
<Editors>
</Editors>
<Publishers>
<Publisher>
<DisplayName>Massachusetts Institute of Technology</DisplayName>
<OrgUnit />
</Publisher>
</Publishers>
<License>http://dspace.mit.edu/handle/1721.1/7582</License>
<Keyword>Electrical Engineering and Computer Science.</Keyword>
<Abstract>As raw compute power of a single chip continues to scale into the multi-teraflop regime, the processor I/O communication fabric must scale proportionally in order to prevent a performance bottleneck. As electrical wires suffer from high channel losses, pin-count constraints, and crosstalk, they are projected to fall short of the demands required by future memory systems. Silicon-photonic optical links overcome the fundamental tradeoffs of electrical wires; dense wavelength division multiplexing (DWDM) - where multiple data channels share a single waveguide or fiber to greatly extend bandwidth density - and the potential to combine at chip-scale with a very large scale integrated (VLSI) CMOS electrical chip make them a promising alternative for next-generation processor I/O. The key device for VLSI photonics is the optical microring resonator, a compact micrometer-scale device enabling energy-efficient modulation, DWDM channel selection, and sometimes even photo-detection. While these advantages have generated considerable interest in silicon-photonics, present-day integration efforts have been limited in scale owing to the difficulty of integration with advanced electronics and the sensitivity of microring resonators to both process and thermal variations. This thesis develops and demonstrates the pieces of a photonically-interconnected processor-to-memory system. We demonstrate a complete optical transceiver platform in a commercial 45 nm SOI process, showing that optical devices can be integrated into an advanced, commercial CMOS SOI process even without any changes to the manufacturing steps of the native process. To show that photonic interconnects are viable even for commoditized and cost-sensitive memory, we develop the first monolithic electronic-photonic links in bulk CMOS. As the stabilization of ring resonators is critical for use in VLSI systems, we contribute to the understanding of process and thermal variations on microring resonators, leading to the demonstration of a complete auto-locking microring tuning system that is agnostic to the transmitted data sequence and suitable for unencoded low-latency processor-to-memory traffic. Finally, the technology and methods developed in this work culminate in the demonstration of the world's first processor chip with integrated photonic interconnects, which uses monolithically integrated photonic devices to optically communicate to main memory.</Abstract>
<Access xmlns="http://purl.org/coar/access_right"
>
</Access>
</Publication>