<?xml version="1.0" encoding="UTF-8"?><?xml-stylesheet type="text/xsl" href="static/style.xsl"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-09-19T06:53:40Z</responseDate><request verb="GetRecord" identifier="oai:dspace.mit.edu:1721.1/99812" metadataPrefix="dim">https://dspace.mit.edu/server/oai/request</request><GetRecord><record><header><identifier>oai:dspace.mit.edu:1721.1/99812</identifier><datestamp>2026-06-16T18:54:43Z</datestamp><setSpec>com_1721.1_7582</setSpec><setSpec>com_1721.1_7581</setSpec><setSpec>col_1721.1_131022</setSpec></header><metadata><dim:dim xmlns:dim="http://www.dspace.org/xmlns/dspace/dim" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:doc="http://www.lyncode.com/xoai" xsi:schemaLocation="http://www.dspace.org/xmlns/dspace/dim http://www.dspace.org/schema/dim.xsd">
   <dim:field mdschema="dc" element="contributor" qualifier="advisor" lang="en_US">Duane S. Boning and Hae-Seung Lee.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="author" lang="en_US">Boo, Hyun Ho</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="other" lang="en_US">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="contributor" qualifier="department">Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="accessioned">2015-11-09T19:50:26Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="available">2015-11-09T19:50:26Z</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="copyright" lang="en_US">2015</dim:field>
   <dim:field mdschema="dc" element="date" qualifier="issued" lang="en_US">2015</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="uri">http://hdl.handle.net/1721.1/99812</dim:field>
   <dim:field mdschema="dc" element="identifier" qualifier="oclc" lang="en_US">927298619</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Cataloged from PDF version of thesis.</dim:field>
   <dim:field mdschema="dc" element="description" lang="en_US">Includes bibliographical references (pages 121-125).</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="abstract" lang="en_US">The performance of switched-capacitor circuits depends highly on the op-amp specifications. In conventional designs, trade-offs in speed, noise, and settling accuracy make it difficult to implement power-efficient switched-capacitor circuits. The problem originates from the inverse relationship between the feedback factor and the signal gain. This thesis proposes the virtual ground reference buffer technique that enhances performance by improving the feedback factor of the op-amp without affecting signal gain. A key concept in the technique is the bootstrapping action of level-shifting buffers. It exploits op-amp-based circuits whose principles are very well understood and the design techniques are mature. The solution ultimately relaxes the required op-amp requirements including unity-gain bandwidth, noise, offset voltage and open-loop gain that would otherwise result in complex design and high power consumption. The concept is demonstrated in a 12-b 250MS/s pipelined ADC.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="statementofresponsibility" lang="en_US">by Hyun Ho Boo.</dim:field>
   <dim:field mdschema="dc" element="description" qualifier="degree" lang="en_US">Ph.D.</dim:field>
   <dim:field mdschema="dc" element="format" qualifier="extent" lang="en_US">125 pages</dim:field>
   <dim:field mdschema="dc" element="language" qualifier="iso" lang="en_US">eng</dim:field>
   <dim:field mdschema="dc" element="publisher" lang="en_US">Massachusetts Institute of Technology</dim:field>
   <dim:field mdschema="dc" element="rights" lang="en_US">M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.</dim:field>
   <dim:field mdschema="dc" element="rights" qualifier="uri" lang="en_US">http://dspace.mit.edu/handle/1721.1/7582</dim:field>
   <dim:field mdschema="dc" element="subject" lang="en_US">Electrical Engineering and Computer Science.</dim:field>
   <dim:field mdschema="dc" element="title" lang="en_US">Virtual ground reference buffer technique in switched-capacitor circuits</dim:field>
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   	&lt;Title>Virtual ground reference buffer technique in switched-capacitor circuits&lt;/Title>
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   	&lt;PublicationDate>2015&lt;/PublicationDate>
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        	&lt;DisplayName>Boo, Hyun Ho&lt;/DisplayName>
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    &lt;Keyword>Electrical Engineering and Computer Science.&lt;/Keyword>
   	&lt;Abstract>The performance of switched-capacitor circuits depends highly on the op-amp specifications. In conventional designs, trade-offs in speed, noise, and settling accuracy make it difficult to implement power-efficient switched-capacitor circuits. The problem originates from the inverse relationship between the feedback factor and the signal gain. This thesis proposes the virtual ground reference buffer technique that enhances performance by improving the feedback factor of the op-amp without affecting signal gain. A key concept in the technique is the bootstrapping action of level-shifting buffers. It exploits op-amp-based circuits whose principles are very well understood and the design techniques are mature. The solution ultimately relaxes the required op-amp requirements including unity-gain bandwidth, noise, offset voltage and open-loop gain that would otherwise result in complex design and high power consumption. The concept is demonstrated in a 12-b 250MS/s pipelined ADC.&lt;/Abstract>
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