Fabrication of capacitors based on silicon nanowire arrays generated by metal-assisted wet chemical etching

Abstract

Capacitors with high capacitance density (capacitance per footprint area) have potential applications in autonomous microsystems that harvest energy from the environment, as they can store and release energy at high rates. Use of high surface-to-volume ratio structures has been demonstrated as an effective way to increase the electrode area, and therefore to improve the capacitance density, while still keeping the footprint area low. The goal of this thesis was to first develop an understanding of the mechanisms of metal assisted wet chemical etching for fabrication of arrays of silicon nanowires, and then use this understanding to build nanowire array on-chip capacitors in silicon substrates, in order to eliminate additional packaging and enable local and efficient energy delivery. Two types of capacitors were investigated: electrostatic metal-oxide-semiconductor (MOS) capacitors for power management, and supercapacitors for energy storage purposes. For both types of devices, enlarged surface area per footprint was achieved by utilizing the arrays of silicon nanowires. Fundamental studies of the roles of metals in metal-assisted chemical etching (MACE) of silicon were conducted. Lithography techniques were used to generate patterns in metal films which when subjected to MACE resulted in formation of ordered arrays of silicon nanowires. Investigation of various metal catalysts showed that Pt is a more active catalyst than Au, while Cu is not stable in the etchant. Tapered silicon nanowires can be generated by adding a layer of Cu between two Au layers, and etching occurs much faster than when a pure Au catalyst is used. While carrying out research on the mechanisms of MACE, we developed a new electrochemical method for formation of arrays of silicon nanowires, metal-assisted anodic etching (MAAE). In this process, the etchant consists of HF alone, and does not include an oxidant. In both processes, HF is used as an etchant. However, in MACE, electronic holes are supplied through reduction of an oxidant (e.g. H₂O₂), while in MAAE, electronic holes are supplied through an external circuit, with anodic contact to either the metal or the silicon. In both contact cases for MAAE, the metal catalyzes the etching process and leads to controlled formation of silicon nanowires, without the need for an oxidant. This discovery, and its analysis, provided new insights into the mechanisms of both MAAE and MACE, and also opened the possibility for use of metal catalyzed electrochemical etching of other materials that cannot survive the HF/oxidant mixture. Processes for fabrication of on-chip capacitors based on silicon nanowires were next developed. We first fabricated on-chip MOS capacitors with nanowire arrays etched using MACE with both single crystal silicon substrates and polycrystalline silicon films. For wires made in both cases, the capacitance density followed a same scaling trend related to their geometries. Epitaxial wafers were used with a post-etch doping process to reduce the series resistance in the devices in order to obtain a better frequency response, as desired for high frequency circuits. To achieve higher capacitance densities for energy storage purposes, we also designed a solid state supercapacitor device based on nanowires etched using MAAE with heavily doped n-type silicon substrates. The silicon nanowires were coated with RuO₂ using atomic layer deposition (ALD) to achieve a high capacitance. In this case, charge is stored through the formation of an electrical double layer and through reversible redox reactions. We showed that the capacitance density of these devices roughly scaled with the increased surface area of silicon nanowire arrays. The solid state supercapacitor achieved a capacitance density of 6.5mF/cm², which is comparable to the best results achieved with other types of on-chip supercapacitors. In contrast with other processes for forming on-chip supercapacitors, the supercapacitors we demonstrated were fabricated using a fully complementary metal-oxide-semiconductor (CMOS) technology compatible process. Moreover, the Si nanowire-based device achieved this high capacitance density without sacrificing power performance compared to the planar device.