Design and implementation of a secure energy-efficient hardware platform for wireless sensor networks

Abstract

Wireless sensor networks are networks of resource-constrained devices that collaborate to sense data about an environment and route it back to a resource-plenty gateway device that is connected to the Internet for processing. Oftentimes, wireless sensor networks are deployed in hazardous or hard to reach areas. For many sensor networks, securing these devices incurs an inhibitively high overhead cost, and tradeoffs must be made between security and energy efficiency, as the energy consumption of these nodes dictates their lifetime. In previous work, a cryptographic accelerator [1] was proposed to speed up and reduce energy consumption of cryptographic primitives. The cryptographic accelerator is used in conjunction with a RISC-V processor to provide the flexibility to implement a wide range of security protocols. This work identifies common security threats in wireless sensor networks, and presents a hardware platform used to demonstrate the energy-efficient, cryptographic capabilities of the RISC-V security chip. We use the platform to test out various secure routing protocols on real hardware, and develop end-to-end energy models of our sensor node platform running these protocols. In developing these models, we seek to demonstrate that the RISC-V security chip can implement network security protocols at relatively little cost in a variety of different network configurations.